M32CSLASH86 datasheet(259/505 Pages) RENESAS

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18. A/D Converter

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18. A/D Converter

The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive cou-

pling amplifier.

The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. It is stored

into the AD00 register only when DMAC operating mode is entered.

Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the

A/D converter. Figures 18.2 to 18.6 show registers associated with the A/D converter.

Table 18.1 A/D Converter Specifications

Item

Specification

A/D Conversion Method

Successive approximation (with a capacitive coupling amplifier)

Analog Input Voltage(1)

0V to AVCC (VCC)

Operating Clock, ØAD(2)

fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8

Resolution

Select from 8 bits or 10 bits

Operating Mode

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

repeat sweep mode 1, multi-port single sweep mode, multi-port repeat sweep

mode 0

Analog Input Pins(3)

34 pins

8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27),

AN15 (AN150 to AN157)

2 extended input pins (ANEX0 and ANEX1)

A/D Conversion Start Condition

• Software trigger

The ADST bit in the AD0CON0 register is set to "1" (A/D conversion started) by

program

• External trigger (re-trigger is enabled)

__________

When a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by

program

• Hardware trigger (re-trigger is enabled)

The timer B2 interrupt request of the three-phase motor control timer functions

(after the ICTB2 counter completes counting) is generated after the ADST bit is

set to "1" by program

Conversion Rate Per Pin

• Without the sample and hold function

8-bit resolution : 49 ØAD cycles

10-bit resolution : 59 ØAD cycles

• With the sample and hold function

8-bit resolution : 28 ØAD cycles

10-bit resolution : 33 ØAD cycles

NOTES:

1. Analog input voltage is not affected by the sample and hold function status.

2. ØAD frequency must be under 16 MHz when VCC=5V.

Without the sample and hold function, the ØAD frequency is 250 kHz or more.

With the sample and hold function, the ØAD frequency is 1 MHz or more.

3. AVCC = VREF = VCC, A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0

and ANEX1)

≤ VCC.

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