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M32C/86 Datasheet(PDF) 261 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 261 Page - Renesas Technology Corp |
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261 / 505 page ![]() Page 238 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 18. A/D Converter ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 18.2 AD0CON0 Register Function A/D0 Control Register 0(1) Bit Name Bit Symbol Symbol Address After Reset AD0CON0 039616 0016 RW RW RW RW RW RW RW RW RW CH0 CH1 CH2 Analog Input Pin Select Bit(2, 3, 8, 9) (i=none, 0, 2, 15) MD0 MD1 TRG CKS0 ADST A/D Operating Mode Select Bit 0(2, 6, 7) A/D Conversion Start Flag Trigger Select Bit Frequency Select Bit 0 : Software trigger 1 : External trigger, hardware trigger(4) 0 : A/D conversion stops 1 : A/D conversion starts(4) (Note 5) 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 b1b0 0 0 0 : ANi0 0 0 1 : ANi1 0 1 0 : ANi2 0 1 1 : ANi3 1 0 0 : ANi4 1 0 1 : ANi5 1 1 0 : ANi6 1 1 1 : ANi7 b2 b3 b4 NOTES: 1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Analog input pins must be set again after changing an A/D operating mode. 3. The CH2 to CH0 bit settings are enabled in one-shot mode and repeat mode. 4. To set the TRG bit to "1", select the cause of trigger by setting the TRG0 bit in the AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". 5. AD frequency must be under 16 MHz when VCC=5V. Combination of the CKS0, CKS1 and CKS2 bits selects AD . 6. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the MD1 and MD0 bits to "102" to enter multi-port single sweep mode and to "112" to enter multi-port repeat sweep mode 0. 7. When the MSS bit is set to "1", the MD1 and MD0 bits cannot be set to "002" or "012". 8. AVCC=VREF=VCC, AD input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AM27, AN150 to AN157, ANEX0, ANEX1) ≤ VCC. 9. Set the PSC_7 bit in the PSC register to "1" to use the P10 pin as an analog input pin. The CKS0 Bit in the AD0CON0 Register The CKS1 Bit in the AD0CON1 Register AD The CKS2 Bit in the AD0CON3 Register 0 1 0 1 0 0 1 0 1 0 1 fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD fAD divided by 8 fAD divided by 6 b7 b6 b5 b4 b3 b2 b1 b0 |
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