M32CSLASH86 datasheet(265/505 Pages) RENESAS

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Page 242

18. A/D Converter

)

(

Function

A/D0 Control Register 4(1)

Bit Name

Bit

Symbol

Address

After Reset

AD0CON4

039216

XXXX 00XX2

MPS10

MPS11

(b1 - b0)

(b7 - b4)

Multi-Port Sweep

Port Select Bit(2)

NOTES:

1. When the AD0CON4 register is rewritten during the A/D conversion, the conversion result is

indeterminate.

2. The MPS11 and MPS10 bits can be set to "102" or "112" in single-chip mode only.

3. When the MSS bit in the AD0CON3 regsiter is set to "0" (multi-port sweep mode disabled), set the

MPS11 and MPS10 bits to "002".

When the MSS bit is set to "1" (multi-port sweep mode enabled), set the MPS11 and MPS10 bits to

"012", "102" or "112".

Reserved Bit

Set to "0".

When read, its content is indeterminate.

Reserved Bit

Set to "0".

When read, its content is indeterminate.

0 0 : (Note 3)

0 1 : AN0 to AN7, AN150 to AN157

1 0 : AN0 to AN7, AN00 to AN07

1 1 : AN0 to AN7, AN20 to AN27

b3 b2

000

0 0

Figure 18.6 AD0CON4 Register and AD00 to AD07 Registers

Function

A/D0 Register i (i =0 to 7)(1, 2, 3, 4, 5)

Symbol

Address

After Reset

AD00

038116 - 038016

00000000 XXXXXXXX2

AD01 to AD03

038316 - 038216, 038516 - 038416, 038716 - 038616

Indeterminate

AD04 to AD06

038916 - 038816, 038B16 - 038A16, 038D16 - 038C16 Indeterminate

AD07

038F16 - 038E16

Indeterminate

8 low-order bits in an A/D conversion result

When read, its content is indeterminate.

In 10-bit mode

In 8-bit mode

: 2 high-order bits in an A/D conversion result

: When read, its content is indeterminate.

b15

NOTES:

1. In DMAC operating mode, register value read by program is indeterminate.

2. Register value is indeterminate when written while the A/D conversion is stopped.

3. Register value is indeterminate if the next A/D conversion result is stored before reading the register.

4. The AD00 register is available in DMAC operating mode. Other registers are indeterminate.

5. In DMAC operating mode and 10-bit mode, set DMAC for a 16-bit transfer.

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