TDA9115 datasheet(21/45 Pages) STMICROELECTRONICS

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TDA9115

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Note 39: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.

Description of I2C Bus switches

Write-to bits

Sad02/D7 - HMoiré

Horizontal Moiré characteristics

0: Adapted to an architecture with EHT gener-

ated in deflection section

1: Adapted to an architecture with separated

deflection and EHT sections

Sad06/D7 - BOutPol

Polarity of B+ drive signal on BOut pin

0: adapted to N type of power MOS - high

level to make it conductive

1: adapted to P type of power MOS - low level

to make it conductive

Sad07/D7 - BOutPh

Phase of start of B+ drive signal on BOut pin

0: Just after horizontal flyback pulse

1: With one of edges of line drive signal on

HOut

pin, selected by BOHEdge bit

Sad08/D7 - EWTrHFr

Tracking of all corrections contained in wave-

form on pin EWOut with Horizontal Frequency

0: Not active

1: Active

Sad16/D0 - HLockEn

Enable of output of Horizontal PLL1 Lock/unlock

status signal on pin HLckVBk

0: Disabled, vertical blanking only on the pin

HLckVBk

1: Enabled

Sad16/D1 - PLL1InhEn

Enable of Inhibition of horizontal PLL1 during

extracted vertical synchronization pulse

0: Disabled, PLL1 is never inhibited

1: Enabled

Sad16/D2 - PLL1Pump

Horizontal PLL1 charge Pump current

0: Slow PLL1, low current

1: Fast PLL1, high current

Sad16/D5 - VSyncSel

Vertical Synchronization input Selection be-

tween the one extracted from composite HV sig-

nal on pin H/HVSyn and the one on pin VSyn.

No effect if VSyncAuto bit is at 1.

0: V. sync extracted from composite signal on

H/HVSyn pin selected

1: V. sync applied on VSyn pin selected

Sad16/D6 - VSyncAuto

Vertical Synchronization input selection Auto-

matic mode. If enabled, the device automatically

selects between the vertical sync extracted from

composite HV signal on pin H/HVSyn and the

one on pin VSyn, based on detection mecha-

nism. If both are present, the one coming first is

kept.

0: Disabled, selection done according to bit

VSyncSel

1: Enabled, the bit VSyncSel has no effect

Sad16/D7 - XRayReset

Reset to 0 of XRay effected with ACK bit of I2C

Bus data transfer into register containing the

XRayReset

bit.

0: No effect

1: Reset with automatic return of the bit to 0

This bit is not latched, it will return to 0 by itself.

Sad17/D0 - BlankMode

Blanking operation Mode

0: Blanking pulse starting with detection of

vertical synchronization pulse and ending

with end of vertical oscillator discharge

XRayReset

0: No effect

1: Reset

VSyncAuto

1:On

VSyncSel

0:Comp

1:Sep

PLL1Pump

1: Fast

0: Slow

PLL1InhEn

1:On

HLockEn

1:On

0:Off(39)

TVM

0:Off(39)

THM

0: Off(39)

BOHEdge

0: Falling

HBOutEn

0: Disable

VOutEn

0: Disable

BlankMode

1: Perm.

Sad

D6D5

D3D2

D1D0

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