BQ3285ECSS datasheet(6/26 Pages) TI

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32kHz Output

The bq3285EC/LC provides for a 32.768kHz output. For

the bq3285EC, the output is always active whenever VCC

is valid (VPFD +tCSR). The bq3285EC output is not af-

fected by the bit settings in Register A. Time-keeping

aspects, however, still require setting OS0-OS2.

The

bq3285LC output is active when the oscillator is turned

on by setting the OSC0-OSC2 bits in Register A.

Interrupts

The bq3285EC/LC allows three individually selected in-

terrupt events to generate an interrupt request. These

three interrupt events are:

The periodic interrupt, programmable to occur once

every 122

µs to 500ms.

The alarm interrupt, programmable to occur once per

second to once per day, is active in battery-backup

mode, providing a “wake-up” feature.

The update-ended interrupt, which occurs at the end

of each update cycle.

Each of the three interrupt events is enabled by an indi-

vidual interrupt-enable bit in register B. When an event

occurs, its event flag bit in register C is set. If the corre-

sponding event enable bit is also set, then an interrupt

request is generated.

The interrupt request flag bit

(INTF) of register C is set with every interrupt request.

Reading register C clears all flag bits, including INTF,

and makes INT high-impedance.

Two methods can be used to process bq3285EC/LC in-

terrupt events:

Enable interrupt events and use the interrupt

request output to invoke an interrupt service routine.

Do not enable the interrupts and use a polling

routine to periodically check the status of the flag

bits.

The individual interrupt sources are described in detail

in the following sections.

bq3285EC/LC

Periodic Interrupt

OSC2

OSC1

OSC0

RS3

RS2

RS1

RS0

Period

Units

010000

None

010000

3.90625

010001

7.8125

010001

122.070

µs

010010

244.141

µs

010010

488.281

µs

010011

976.5625

µs

010011

1.95315

010100

3.90625

010100

7.8125

010101

15.625

010101

31.25

010110

62.5

010110

125

010111

250

010111

500

011

same as above defined

by RS3–RS0

Table 3. Periodic Interrupt Rate

July 1996

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