BQ3285ECSS datasheet(8/26 Pages) TI

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Power-Down/Power-Up Cycle

The bq3285EC and bq3285LC power-up/power-down cy-

cles are different. The bq3285LC continuously monitors

VCC for out-of-tolerance. During a power failure, when

VCC falls below VPFD (2.53V typical), the bq3285LC write-

protects the clock and storage registers. The power source

is switched to BC when VCC is less than VPFD and BC is

greater than VPFD, or when VCC is less than VBC and VBC

is less than VPFD. RTC operation and storage data are

sustained by a valid backup energy source. When VCC is

above VPFD, the power source is VCC. Write-protection con-

tinues for tCSR time after VCC rises above VPFD.

The bq3285EC continuously monitors VCC for out-of-

tolerance. During a power failure, when VCC falls below

VPFD (4.17V typical), the bq3285EC write-protects the

clock and storage registers. When VCC is below VBC (3V

typical), the power source is switched to BC. RTC opera-

tion and storage data are sustained by a valid backup

energy source.

When VCC is above VBC, the power

source is VCC. Write-protection continues for tCSR time

after VCC rises above VPFD.

Control/Status Registers

The four control/status registers of the bq3285EC/LC

are accessible regardless of the status of the update cy-

cle (see Table 4).

The frequency of the periodic event rate.

Oscillator operation.

Time-keeping

Status of the update cycle.

RS0–RS3 - Frequency Select

These bits select the periodic interrupt rate, as shown in

Table 3.

OS0–OS2 - Oscillator Control

These three bits control the state of the oscillator and

divider stages. A pattern of 010 or 011 enables RTC op-

eration by turning on the oscillator and enabling the fre-

quency divider. This pattern must be set to turn the os-

cillator on for the bq3285LC and to ensure that the

bq3285EC/LC will keep time in battery-backup mode. A

pattern of 11X turns the oscillator on, but keeps the fre-

quency divider disabled. When 010 is written, the RTC

begins its first update after 500ms.

UIP - Update Cycle Status

This read-only bit is set prior to the update cycle. When

UIP equals 1, an RTC update cycle may be in progress.

UIP is cleared at the end of each update cycle. This bit

is also cleared when the update transfer inhibit (UTI)

bit in register B is 1.

bq3285EC/LC

76543210

UIP

OS2

OS1

OS0

RS3

RS2

RS1

RS0

76543210

----

RS3

RS2

RS1

RS0

76543210

OS2

OS1

OS0

----

76543210

UIP

-------

July 1996

Reg.

Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB)

0 (LSB)

Yes

UIP

OS2

OS1

OS0 na

RS3

RS2

RS1

RS0

Yes

UTI

PIE

AIE

UIE

DSE na

Yes

INTF

Yes

VRT

-0-0-

0-0-0

Notes:

na = not affected.

Except bit 7.

Table 4. Control/Status Registers

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