MCP662-ESLASHMF datasheet(23/42 Pages) MICROCHIP

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DS22194A-page 23

MCP661/2/3/5

The power de-rating across temperature for an op amp

in a particular package can be easily calculated

(assuming equal power dissipations):

EQUATION 4-5:

Several techniques are available to reduce

ΔTJA for a

given POAmax:

• Lower

θJA

- Use another package

- PCB layout (ground plane, etc.)

- Heat sinks and air flow

• Reduce POAmax

- Increase RL

- Limit IOUT (using RSER)

- Decrease VDD

4.3

Distortion

Differential Gain (DG) and Differential Phase (DP)

refer to the non-linear distortion produced by a NTSC

(or PAL) video component. Table 1-2 and Figure 2-34

show the typical performance of the MCP661,

configured as a gain of +2 amplifier (see Figure 4-10),

when driving one back-matched video load (150

Ω, for

Ω cable). Our tests use a sine wave at NTSC’s color

sub-carrier frequency of 3.58 MHz, with a 0.286VP-P

magnitude. The DC input voltage is changed over a

+0.7V range (positive video) or a -0.7V range (negative

video).

DG is the peak-to-peak change in the AC gain

magnitude (color hue), as the DC level (luminance) is

changed, in units of %. DP is the peak-to-peak change

in the AC gain phase (color saturation), as the DC level

(luminance) is changed, in units of °.

4.4

Improving Stability

4.4.1

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-6) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-6:

Output Resistor, RISO

stabilizes large capacitive loads.

Figure 4-7 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN =+2 V/V).

FIGURE 4-7:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP661/2/3/5 SPICE macro

model are helpful.

TJmax –TA

POAmax ≤

Where:

TJmax = absolute max. junction temperature

RISO

VOUT

MCP66X

100

1.E-11

1.E-10

1.E-09

1.E-08

Normalized Capacitance; CL/GN (F)

GN = +1

GN ≥ +2

10p

100p

10n

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