MCP662-ESLASHMF datasheet(24/42 Pages) MICROCHIP

24 / 42 page

MCP661/2/3/5

DS22194A-page 24

4.4.2

GAIN PEAKING

Figure 4-8 shows an op amp circuit that represents

non-inverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG rep-

resent the total capacitance at the input pins; they

include the op amp’s common mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

FIGURE 4-8:

Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

CG also reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing CG or RF.

CN and RN form a low-pass filter that affects the signal

at VP. This filter has a single real pole at 1/(2πRNCN).

The largest value of RF that should be used depends

on noise gain (see GN in Section 4.4.1 “Capacitive

Loads”), CG and the open-loop gain’s phase shift.

Figure 4-9 shows the maximum recommended RF for

several CG values. Some applications may modify

these values to reduce either output loading or gain

peaking (step response overshoot).

FIGURE 4-9:

Maximum recommended RF

vs. Gain.

Figure 2-35 and Figure 2-36 show the small signal and

large signal step responses at G = +1 V/V. The unity

gain buffer usually has RF =0Ω and RG open.

Figure 2-37 and Figure 2-38 show the small signal and

large signal step responses at G = -1 V/V. Since the

noise gain is 2 V/V and CG ≈ 10 pF, the resistors were

chosen to be RF =RG = 401Ω and RN =200Ω.

It is also possible to add a capacitor (CF) in parallel with

RF to compensate for the de-stabilizing effect of CG.

This makes it possible to use larger values of RF. The

conditions for stability are summarized in Equation 4-6.

EQUATION 4-6:

4.5

MCP663 and MCP665 Chip Select

The MCP663 is a single amplifier with Chip Select

(CS). When CS is pulled high, the supply current drops

to 1 µA (typical) and flows through the CS pin to VSS.

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 M

Ω (typical)

pulldown resistor connected to VSS, so it will go low if

the CS pin is left floating. Figure 1-1, Figure 2-43 and

Figure 2-44 show the output voltage and supply current

response to a CS pulse.

The MCP665 is a dual amplifier with two CS pins; CSA

controls op amp A and CSB controls op amp B. These

op amps are controlled independently, with an enabled

quiescent current (IQ) of 6 mA/amplifier (typical) and a

disabled IQ of 1 µA/amplifier (typical). The IQ seen at

the supply pins is the sum of the two op amps’ IQ; the

typical value for the MCP665’s IQ will be 2 µA, 6 mA or

12 mA when there are 0, 1 or 2 amplifiers enabled,

respectively.

4.6

Power Supply

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

supplies does not prove to be a problem.

VOUT

MCP66X

1.E+02

1.E+03

1.E+04

1.E+05

110

100

Noise Gain; GN (V/V)

GN > +1 V/V

100

10k

100k

CG = 10 pF

CG = 32 pF

CG = 100 pF

CG = 320 pF

CG = 1 nF

GBWP

()

⁄

, G

≤

We need:

F RG

⁄

G CF

⁄

πR

FCF

()

⁄

F GN1 GN2

⁄

()

Given:

GBWP

()

⁄

, G

≤

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