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MPC5200B Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

Part # MPC5200B
Description  SDRAM/DDR Memory Controller
PDF  72 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200B Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 4
30
Freescale Semiconductor
Figure 14. PIO Mode Timing
Table 28. Multiword DMA Timing Specifications
Sym
Multiword DMA Timing Parameters
Min/Max
Mode 0(ns)
Mode 1(ns)
Mode 2(ns)
SpecID
t0
Cycle Time
min
480
150
120
A8.12
tC
DMACK to DMARQ delay
max
—
—
—
A8.13
tD
DIOR/DIOW pulse width (16-bit)
min
215
80
70
A8.14
tE
DIOR data access
max
150
60
50
A8.15
tG
DIOR/DIOW data setup
min
100
30
20
A8.16
tF
DIOR data hold
min
5
5
5
A8.17
tH
DIOW data hold
min
20
15
10
A8.18
tI
DMACK to DIOR/DIOW setup
min
0
0
0
A8.19
tJ
DIOR/DIOW to DMACK hold
min
20
5
5
A8.20
tKr
DIOR negated pulse width
min
50
50
25
A8.21
tKw
DIOW negated pulse width
min
215
50
25
A8.22
tLr
DIOR to DMARQ delay
max
120
40
35
A8.23
tLw
DIOW to DMARQ delay
max
40
40
35
A8.24
WDATA
RDATA
IORDY
t0
t1
t2
t3
t4
t5
t6
t9
tA
tB
CS[0]/CS[3]/DA[2:0]
DIOR/DIOW



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