MPC5200B_10 datasheet(52/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A15.46

SCK pulse width, 50% SCK duty cycle

15.0

—

A15.47

Slave select clock delay, programable in the PSC CCS register

30.0

—

A15.48

Output data valid

—

8.9

A15.49

Input Data setup time

6.0

—

A15.50

Input Data hold time

1.0

—

A15.51

Slave disable lag time

—

8.9

A15.52

Sequential Transfer delay, programable in the PSC CTUR / CTLR

15.0

—

A15.53

Clock falling time

—

7.9

A15.54

Clock rising time

—

7.9

A15.55

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

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