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ADT7462ACPZ-R7 Datasheet(PDF) 70 Page - ON Semiconductor

Part # ADT7462ACPZ-R7
Description  Flexible Temperature, Voltage Monitor, and System Fan Controller
PDF  81 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADT7462ACPZ-R7 Datasheet(HTML) 70 Page - ON Semiconductor

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Table 60. Register 0x26 — PWM3, PWM4 Frequency (Note 1)
Bit
Name
R/W
Description
0
Min 3
R/W
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM3 is off
(0% duty cycle) or at minimum PWM3 duty cycle when the controlling temperature is below its
TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM3 duty cycle below
TMIN − hysteresis.
1
Min 4
R/W
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM4 is off
(0% duty cycle) or at minimum PWM4 duty cycle when the controlling temperature is below its
TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM4 duty cycle below
TMIN − hysteresis.
[4:2]
Low Freq 3
R/W
These bits set the frequency of PWM3 when configured in low frequency mode.
000 = 11 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
[7:5]
Low Freq 4
R/W
These bits set the frequency of PWM4 when configured in low frequency mode.
000 = 11 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
1. POR = 0x90, Lock = Y, SW Reset = Y.
Table 61. Minimum PWMx Duty Cycle (Note 1)
Register Address
R/W
Description
POR Default
0x28
R/W
Minimum PWM1 duty cycle
0x80
0x29
R/W
Minimum PWM2 duty cycle
0x80
0x2A
R/W
Minimum PWM3 duty cycle
0x80
0x2B
R/W
Minimum PWM4 duty cycle
0x80
1. Lock = Y, SW Reset = Y.
Table 62. Register 0x2C — Maximum PWM Duty Cycle (Note 1)
Bit
Name
R/W
Description
[7:0]
Maximum PWM
Duty Cycle
R/W
This register sets the maximum % duty cycle output in automatic fan speed control mode for all
four PWM outputs.
1. POR = 0xC0, Lock = Y, SW Reset = Y.
Table 63. Register 0x30 — Thermal Mask Register 1 (Note 1)
Bit
Name
R/W
Description
0
Reserved
R/W
Reserved for future use.
1
Local Temp
R/W
1 masks ALERTs for an out−of−limit condition on the local temperature channel.
2
Remote 1 Temp
R/W
1 masks ALERTs for an out−of−limit condition on the Remote 1 temperature channel.
3
Remote 2 Temp
R/W
1 masks ALERTs for an out−of−limit condition on the Remote 2 temperature channel.
4
Remote 3 Temp
R/W
1 masks ALERTs for an out−of−limit condition on the Remote 3 temperature channel.
5
Diode 1 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 1 channel.
6
Diode 2 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 2 channel.
7
Diode 3 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 3 channel.
1. POR = 0x00, Lock = N, SW Reset = Y.



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