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ADT7462ACPZ-R7 Datasheet(PDF) 71 Page - ON Semiconductor |
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ADT7462ACPZ-R7 Datasheet(HTML) 71 Page - ON Semiconductor |
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71 / 81 page ![]() ADT7462 http://onsemi.com 71 Table 64. Register 0x31 — Thermal Mask Register 2 (Note 1) Bit Name R/W Description 0 THERM1 % R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 THERM1 Assert R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 2 THERM1 State R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 3 THERM2 % R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 4 THERM2 Assert R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 5 THERM2 State R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 6 VRD1_Assert R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 7 VRD2_Assert R/W 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 1. POR = 0xC0, Lock = N, SW Reset = Y. Table 65. Register 0x32 — Voltage Mask Register 1 (Note 1) Bit Name R/W Description 0 +12V1 R/W 1 masks ALERTs for the corresponding interrupt status bit. 1 +12V2 R/W 1 masks ALERTs for the corresponding interrupt status bit. 2 +12V3 R/W 1 masks ALERTs for the corresponding interrupt status bit. 3 +3.3V R/W 1 masks ALERTs for the corresponding interrupt status bit. 4 Pin 15 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 5 Pin 19 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 6 +5V R/W 1 masks ALERTs for the corresponding interrupt status bit. 7 Pin 23 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 1. POR = 0x00, Lock = N, SW Reset = Y. Table 66. Register 0x33 — Voltage Mask Register 2 (Note 1) Bit Name R/W Description [2:0] Reserved R/W Reserved for future use. 3 Pin 24 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 4 Pin 25 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 5 Pin 26 Voltage R/W 1 masks ALERTs for the corresponding interrupt status bit. 6 +1.5V2 (3GIO) R/W 1 masks ALERTs for the corresponding interrupt status bit. 7 +1.5V1 (ICH) R/W 1 masks ALERTs for the corresponding interrupt status bit. 1. POR = 0x00, Lock = N, SW Reset = Y. Table 67. Register 0x34 — Fan Mask Register (Note 1) Bit Name R/W Description 0 Fan 1 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 1 Fan 2 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 2 Fan 3 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 3 Fan 4 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 4 Fan 5 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 5 Fan 6 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 6 Fan 7 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 7 Fan 8 Fault R/W 1 masks ALERTs for the corresponding interrupt status bit. 1. POR = 0x00, Lock = N, SW Reset = Y. |
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