ADT7476ARQZ-R7 datasheet(63/67 Pages) ONSEMI

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ADT7476

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Table 47. Register 0x78 — Configuration Register 3 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[0]

ALERT

R/W

ALERT = 1, Pin 10 (PWM2/ SMBALERT) is configured as an SMBALERT interrupt output to

indicate out−of−limit error conditions.

ALERT = 0, Pin 10 (PWM2/ SMBALERT) is configured as the PWM2 output.

[1]

THERM/

2.5V

R/W

THERM = 1 enables THERM functionality on Pin 22 and Pin 14, if Pin 14 is configured as

THERM, determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM

is asserted, if the fans are running and the BOOST bit is set, then the fans run at full speed.

Alternatively, THERM can be programmed so that a timer is triggered to time how long THERM

has been asserted.

THERM = 0 enables 2.5V measurement on Pin 22 and disables THERM. If Bits [5:7] of

Configuration Register 5 are set, THERM is bidirectional. If they are 0, THERM is a timer input

only.

Pin14FUNC

THERM/2.5 V

Pin 22

Pin 14

+2.5 VIN

THERM

+2.5 VIN

THERM

TACH4

THERM

SMBALERT

GPIO6

TACH4

THERM

SMBALERT

GPIO6

[2]

BOOST

R/W

When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the

maximum programmed duty cycle for fail−safe cooling.

[3]

FAST

R/W

FAST = 1 enables fast TACH measurements on all channels. This increases the TACH

measurement rate from once per second to once every 250 ms (4x).

[4]

DC1

R/W

DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be

driven by dc. Setting this bit prevents pulse stretching because it is not required for dc driven

motors.

[5]

DC2

R/W

DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be

driven by dc. Setting this bit prevents pulse stretching because it is not required for dc driven

motors.

[6]

DC3

R/W

DC3 = 1 enables TACH measurements to be continuously made on TACH3. Fans must be

driven by dc. Setting this bit prevents pulse stretching because it is not required for dc driven

motors.

[7]

DC4

R/W

DC4 = 1 enables TACH measurements to be continuously made on TACH4. Fans must be

driven by dc. Setting this bit prevents pulse stretching because it is not required for dc driven

motors.

1. This register become read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to to this register have no

effect.

Table 48. Register 0x79 — THERM Timer Status Register (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[7:1]

TMR

Read−only

Times how long THERM input is asserted. These seven bits read 0 until the THERM

assertion time exceeds 45.52 ms.

[0]

ASRT/

TMR0

Read−only

This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM

assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8−bit TMR

reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back

with a resolution of 22.76 ms.

Table 49. Register 0x7A — THERM Timer Limit Register (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[7:0]

LIMT

R/W

Sets maximum THERM assertion length allowed before an interrupt is generated. This is an

8−bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to

5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of

Interrupt Status Register 2 (0x42) is set. If the limit value is 0x00, an interrupt is generated

immediately on the assertion of the THERM input.

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