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IMX28CEC Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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IMX28CEC Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 70 page  i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 33 3.5.3.3 DDR2 Input AC Timing Figure 7 and Table 37 show input AC timing for standard DDR2 and LVDDR2. Figure 7. DDR2 Input AC Timing DDR13 DQS output high pulse width tDQSH 0.5 tCK –0.5 0.5 tCK + 0.5 ns DDR14 DQS output low pulse width tDQSL 0.5 tCK –0.5 0.5 tCK + 0.5 ns DDR15 DQ & DQM output setup time relative to DQS tDS 1/4 tCK –0.8 1/4 tCK –0.5 ns DDR16 DQ & DQM output hold time relative to DQS tDH 1/4 tCK –0.8 1/4 tCK –0.5 ns Table 37. DDR2 Input AC Timing ID Description Symbol Min Max Unit DDR20 Positive DQS latching edge to associated CK edge tDQSCK –0.5 0.5 ns DDR21 DQS to DQ input skew tDQSQ 0.25 tCK –0.85 0.25 tCK –0.5 ns DDR22 DQS to DQ input hold time tQH 0.25 tCK +0.75 0.25 tCK + 1 ns Table 36. DDR Output AC Timing (continued) ID Description Symbol Min Max Unit EMI_CLK EMI_CLKN EMI_DQS DDR21 DDR22 d0 DDR20 d1 d2 d3 EMI_DQ EMI_DQSN |
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