IMX28CEC datasheet(7/70 Pages) FREESCALE

7 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

BCH

Bit-correcting

ECC

accelerator

Connectivity

peripherals

The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder

module is capable of correcting from 2 to 20 single bit errors within a block of

data no larger than about 900 bytes (512 bytes is typical) in applications such

as protecting data and resources stored on modern NAND flash devices.

BSI

Boundary

Scan Interface

Connectivity

peripherals

The boundary scan interface is provided to enable board level testing.

There are five pins on the device which is used to implement the IEEE Std

1149.1™ boundary scan protocol.

CLKCTRL

Clock control

module

Clocks

The clock control module, or CLKCTRL, generates the clock domains for all

components in the i.MX28 system. The crystal clock or PLL clock are the two

fundamental sources used to produce most of the clock domains. For lower

performance and reduced power consumption, the crystal clock is selected.

The PLL is selected for higher performance requirements but requires

increased power consumption. In most cases, when the PLL is used as the

source, a Phase Fractional Divider (PFD) can be programmed to reduce the

PLL clock frequency by up to a factor of 2.

DCP

Data

co-processor

Security

This module provides support for general encryption and hashing functions

typically used for security functions. Because its basic job is moving data

from memory to memory, it also incorporates a memory-copy (memcopy)

function for both debugging and as a more efficient method of copying data

between memory blocks than the DMA-based approach.

DFLPT

Default

first-level page

table

System control

The DFLPT provides a unique method of implementing the ARM MMU

first-level page table (L1PT) using a hardware-based approach.

DIGCTL

Digital control

and on-chip

RAM

System control

The digital control module includes sections for controlling the SRAM, the

performance monitors, high-entropy pseudo-random number seed,

free-running microseconds counter, and other chip control functions.

DUART

Debug UART

Connectivity

peripherals

The Debug UART performs the following data conversions:

• Serial-to-parallel conversion on data received from a peripheral device

• Parallel-to-serial conversion on data transmitted to the peripheral device

EMI

External

memory

interface

Connectivity

peripherals

The i.MX28 supports off-chip DRAM storage through the EMI controller,

which is connected to the four internal AHB/AXI busses. The EMI supports

multiple external memory types, including:

• 1.8-V Mobile DDR1 (LP-DDR1)

• Standard 1.8-V DDR2

• Low Voltage 1.5-V DDR2 (LV-DDR2)

ENET

Ethernet MAC

Controller

Connectivity

peripherals

Ethernet MAC controller connected to the uDMA (unified DMA). Supports

10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also

supports RMII or MII connectivity.

FlexCAN(2)

Controller

area network

module

Connectivity

peripherals

The Controller Area Network (CAN) protocol is a message based protocol

used for serial data. It was designed specifically for automotive but is also

used in industrial control and medical applications. The serial data bus runs

at 1 Mbps.

GPMI

General-pur-

pose media

interface

Connectivity

peripherals

The General-Purpose Media Interface (GPMI) controller is a flexible NAND

flash controller with 8-bit data width, up to 50-MBps I/O speed and individual

chip select and DMA channels for up to 8 NAND devices. It also provides a

interface to 20-bit BCH for ECC.

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

IMX28CEC Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

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