SC667201MMG3 datasheet(52/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Pinout and signal description

BOOTCFG[0:1]

SIU – Configuration

Two BOOTCFG signals are implemented in MPC5642A

MCUs.

The BAM program uses the BOOTCFG0 bit to determine

where to read the reset configuration word, and whether to

initiate a FlexCAN or eSCI boot.

The BOOTCFG1 pin is sampled during the assertion of the

RSTOUT signal, and the value is used to update the RSR and

the BAM boot mode.

See reference manual section “Reset Configuration Half Word

(RCHW)” for details on the RCHW. The table “Boot Modes” in

reference manual section “BAM Program Operation” defines

the boot modes specified by the BOOTCFG1 pin.

The following values are for BOOTCFG[0:1}:

00: Boot from internal flash memory

01: FlexCAN/eSCI boot

10: Boot from external memory using calibration bus

11: Reserved

Note: For the 176-pin QFP and 208-ball BGA packages

BOOTCFG[0] is always 0 since the EBI interface is not

available.

WKPCFG

SIU – Configuration

The WKPCFG pin is applied at the assertion of the internal

reset signal (assertion of RSTOUT), and is sampled four clock

cycles before the negation of the RSTOUT pin.

The value is used to configure whether the eTPU and eMIOS

pins are connected to internal weak pull up or weak pull down

devices after reset. The value latched on the WKPCFG pin at

reset is stored in the Reset Status Register (RSR), and is

updated for all reset sources except the Debug Port Reset and

Software External Reset.

0: Weak pulldown applied to eTPU and eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS pins at reset

ETRIG[2:3]

SIU – eQADC Triggers

External signal eTRIGx triggers eQADC CFIFOx

GPIO[206] ETRIG0

(Input)

SIU – eQADC Triggers

External signal eTRIGx triggers eQADC CFIFOx

GPIO[207] ETRIG1

(Input)

SIU – eQADC Triggers

External signal eTRIGx triggers eQADC CFIFOx

IRQ[0:5]

IRQ[7:15]

SIU – External Interrupts

The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX

Select Register 1 is used to select the IRQ[0:15] pins as inputs

to the IRQs.

See reference manual section “External IRQ Input Select

NMI

SIU – External Interrupts

Non-Maskable Interrupt

Table 5. Signal details (continued)

Signal

Module or function

Description

SC667201MMG3 Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc

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