SC667201MMG3 datasheet(87/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Electrical characteristics

NOTE

The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a

read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write

access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG

Update-DR state. This prevents the access from being performed and therefore will not

signal its completion via the READY (RDY) output unless the JTAG controller receives an

additional TCK. In addition, EVTI is not latched into the device unless there are clock

transitions on TCK.

The tool/debugger must provide at least one TCK clock for the EVTI signal to be

recognized by the MCU. When using the RDY signal to indicate the end of a Nexus

read/write access, ensure that TCK continues to run for at least one TCK after leaving the

Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or

by continuing with the next Nexus/JTAG command. Expect the effect of EVTI and RDY

to be delayed by edges of TCK.

RDY is not available in all device packages.

4tTMSS, tTDIS CC D TMS, TDI Data Setup Time

—

5tTMSH, tTDIH CC D TMS, TDI Data Hold Time

—

6tTDOV

CC D TCK Low to TDO Data Valid

—

222

7tTDOI

CC D TCK Low to TDO Data Invalid

—

8tTDOHZ

CC D TCK Low to TDO High Impedance

—

9tJCMPPW

CC D JCOMP Assertion Time

100

—

tJCMPS

CC D JCOMP Setup Time to TCK Low

—

tBSDV

CC D TCK Falling Edge to Output Valid

—

tBSDVZ

CC D TCK Falling Edge to Output Valid out of High Impedance

—

tBSDHZ

CC D TCK Falling Edge to Output High Impedance

—

tBSDST

CC D Boundary Scan Input Valid to TCK Rising Edge

253

—ns

tBSDHT

CC D TCK Rising Edge to Boundary Scan Input Invalid

253

—ns

1 JTAG timing specified at V

DD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to

Low-Swing mode, TA = TL to TH, CL = 30 pF, SRC = 0b11. These specifications apply to JTAG boundary scan only.

See Table 38 for functional specifications.

2 Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.

3 For 20 MHz TCK.

Table 37. JTAG pin AC electrical characteristics1 (continued)

Symbol

Characteristic

Value

Unit

Min

Max

SC667201MMG3 Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc

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