STM32L151VD datasheet(97/140 Pages) STMICROELECTRONICS

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Electrical characteristics

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6.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 50 are derived from tests

performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL

compliant.

Table 50.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

TTL ports

2.7 V

≤ VDD≤ 3.6 V

VSS - 0.3

0.8

VIH

Standard I/O input high level voltage

2(1)

-VDD+0.3

FT(2) I/O input high level voltage

5.5V

VIL

Input low level voltage

CMOS ports

1.65 V

≤ VDD≤ 3.6 V

–0.3

0.3VDD

(3)

VIH

Standard I/O Input high level voltage

CMOS ports

1.65 V

≤ VDD≤ 3.6 V

0.7 VDD

(3)(4)

-VDD+0.3

FT(5) I/O input high level voltage

CMOS ports

1.65 V

≤ VDD≤ 2.0 V

-5.25

CMOS ports

2.0 V

≤ VDD≤ 3.6 V

-5.5

Vhys

Standard I/O Schmitt trigger voltage

hysteresis(6)

10% VDD

(7)

Ilkg

Input leakage current (8)(3)

VSS ≤ VIN ≤ VDD

I/Os with LCD

±50

VSS ≤ VIN ≤ VDD

I/Os with analog

switches

±50

VSS ≤ VIN ≤ VDD

I/Os with analog

switches and LCD

±50

VSS ≤ VIN ≤ VDD

I/Os with USB

TBD

VSS ≤ VIN ≤ VDD

Standard I/Os

±50

RPU

Weak pull-up equivalent resistor(9)(3)

VIN = VSS

RPD

Weak pull-down equivalent resistor(9)(3)

VIN = VDD

CIO

I/O pin capacitance

Guaranteed by design.

FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled.

Tested in production

0.7VDD for 5V-tolerant receiver

FT = Five-volt tolerant.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

With a minimum of 200 mV. Based on characterization, not tested in production.

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