AT90PWM2 datasheet(19/365 Pages) ATMEL

19 / 365 page

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Memories

This section describes the different memories in the AT90PWM2/2B/3/3B. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In addition,

the AT90PWM2/2B/3/3B features an EEPROM Memory for data storage. All three memory

spaces are linear and regular.

6.1

In-System Reprogrammable Flash Program Memory

The AT90PWM2/2B/3/3B contains 8K bytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

4K x 16. For software security, the Flash Program memory space is divided into two sections,

Boot Program section and Application Program section.

The F lash memory has an endurance of at least 10,000 write/erase cycles. The

AT90PWM2/2B/3/3B Program Counter (PC) is 12 bits wide, thus addressing the 4K program

memory locations. The operation of Boot Program section and associated Boot Lock bits for

software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Pro-

gramming” on page 265. “Memory Programming” on page 280 contains a detailed description

on Flash programming in SPI or Parallel programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory.

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

Figure 6-1.

Program Memory Map

6.2

SRAM Data Memory

Figure 6-2 shows how the AT90PWM2/2B/3/3B SRAM Memory is organized.

0x0000

0x0FFF

Program Memory

Application Flash Section

Boot Flash Section

AT90PWM2 Datasheet(PDF) 19 Page - ATMEL Corporation