AT90PWM2 datasheet(43/365 Pages) ATMEL

43 / 365 page

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Notes:

1. Only recommended with external crystal or resonator selected as clock source.

2. Only level interrupt.

8.6

Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-

als to reduce power consumption. The current state of the peripheral is frozen and the I/O

registers can not be read or written. Resources used by the peripheral when stopping the clock

will remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

A full predictible behaviour of a peripheral is not guaranteed during and after a cycle of stopping

and starting of its clock. So its recommended to stop a peripheral before stopping its clock with

PRR register.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.

8.6.1

Power Reduction Register - PRR

Note:

PRPSC1 is not used on AT90PWM2/2B

• Bit 7 - PRPSC2: Power Reduction PSC2

Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this

module. When waking up the PSC2 again, the PSC2 should be re initialized to ensure proper

operation.

Table 8-2.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillator

Wake-up Sources

Sleep

Mode

Idle

XXX

ADC

Noise

Reduction

X(2)

Power-

down

X(2)

Standby(1)

XX(2)

Bit

543

PRPSC2

PRPSC1(

Note:)

PRPSC0

PRTIM1

PRTIM0

PRSPI

PRUSART

PRADC

PRR

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 43 Page - ATMEL Corporation

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