AT45CS1282_14 datasheet(9/33 Pages) ATMEL

9 / 33 page

AT45CS1282 [Preliminary]

3447A–DFLSH–2/04

Security Register

The AT45CS1282 contains a specialized register that can be used for security purposes

in system design. The Security Register is a unique 128-byte register that is divided into

two portions. The first 64 bytes (byte 0 to byte 63) of this register are allocated as a one-

time user programmable space. Once these 64 bytes have been programmed, they

should not be reprogrammed. The remaining 64 bytes of this register (byte 64 to byte

127) are factory programmed by Atmel and will contain a unique number for each

device. The factory programmed data is fixed and cannot be changed.

The Security Register can be read by clocking in opcode 77H to the device followed by

four address bytes (which are comprised of 21 don’t care bits plus 11 byte address bits)

and a series of don’t care clock cycles (24 if using the serial interface and 19 if using the

8-bit interface). The Security Register Read can be terminated by asserting CS low to

high after the 128-byte security register has been read out. The continuation of clocking

past that will result in indeterminate data on the output. See the opcode table on page

13 for this mode.

To program the first 64 bytes of the Security Register, a two step sequence must be

used. The first step requires that the user loads the desired data into Buffer 1 by using

the Buffer 1 Write operation (opcode 84H – see Buffer Write description). The user

should specify the starting buffer address as location zero and should write a full

64 bytes of information into the buffer. Otherwise, the first 64 bytes of the buffer may

contain data that was previously stored in the buffer. It is not necessary to fill the remain-

ing 992 bytes (byte locations 64 through 1055) of the buffer with data. After the Buffer 1

Write operation has been completed, the Security Register can be subsequently pro-

grammed by reselecting the device and clocking in opcode 9AH into the device followed

by four don’t care bytes (32 clock cycles if using the serial interface and four clock

cycles if using the 8-bit interface). After the final don’t care clock cycle has been

completed, a low-to-high transition on the CS pin will cause the device to initiate an

internally self-timed program operation in which the contents of Buffer 1 will be pro-

grammed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be

programmed into the Security Register; the remaining 992 bytes of the buffer will be

ignored. The Security Register program operation should take place in a maximum time

of t

Operation Mode

Summary

The modes described can be separated into two groups – modes that make use of the

Flash memory array (Group A) and modes that do not make use of the Flash memory

array (Group B).

Group A modes consist of:

Main Memory Page Read

Continuous Array Read

Main Memory Page to Buffer 1 (or 2) Transfer

Main Memory Page to Buffer 1 (or 2) Compare

Buffer 1 (or 2) to Main Memory Page Program

Sector 0a Erase

Sector 0b-63 Erase

Group B modes consist of:

Buffer 1 (or 2) Read

Buffer 1 (or 2) Write

Status Register Read

AT45CS1282 Datasheet(PDF) 9 Page - ATMEL Corporation

AT45CS1282 Datasheet(HTML) 9 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL