AT45CS1282_14 datasheet(1/33 Pages) ATMEL

Part #	AT45CS1282

Description	Sector Erase Architecture

PDF	33 Pages

Scroll/Zoom	100%

Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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1

Features

• Single 2.7V - 3.6V Supply

• Dual-interface Architecture

–RapidS

™ Serial Interface: 50 MHz Maximum Clock Frequency

(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)

–Rapid8

™ 8-bit Interface: 20 MHz Maximum Clock Frequency

• Page Program

– 16,384 Pages (1,056 Bytes/Page) Main Memory

• Sector Erase Architecture

– Sixty-three 270,336-byte Sectors

– One 261,888-byte Sector

– One 8,488-byte Sector

• Two 1056-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming the Flash Array

• Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

• Low-power Dissipation

– 10 mA Active Read Current Typical – Serial Interface

– 12 mA Active Read Current Typical – 8-bit Interface

– 15 µA CMOS Standby Current Typical

• Hardware Data Protection

• Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

• JEDEC Standard Manufacturer and Device ID Read

• 100 Program/Erase Cycles Per Sector Minimum

• Data Retention – 10 Years

• Commercial Temperature Range

Description

The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory

ideally suited for infrequent code shadowing applications. This device utilizes Atmel’s

e

-STAC™ Multi-Level Cell (MLC) memory technology, which allows a single cell to

128-megabit

2.7-volt

Dual-interface

Code Shadow

DataFlash®

AT45CS1282

Preliminary

™

Note:

*Optional Use – See pin description text

for connection information.

Pin Configurations

Pin Name

Function

CS

Chip Select

SCK/CLK

Serial Clock/Clock

SI

Serial Input

SO

Serial Output

I/O7 - I/O0

8-bit Input/Output

WP

Hardware Page Write

Protect Pin

RESET

Chip Reset

RDY/BUSY

Ready/Busy

SER/BYTE

Serial/8-bit Interface

Control

TSOP Top View: Type 1

CBGA Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

NC

RDY/BUSY

RESET

WP

NC

VCC

GND

NC

CS

SCK

SI*

SO*

NC

I/O7*

I/O6*

I/O5*

I/O4*

VCCP*

GNDP*

I/O3*

I/O2*

I/O1*

I/O0*

SER/BYTE*

CLK

NC

A

B

C

D

E

F

G

H

J

1

23

4

5

NC

I/O2

I/O1

I/O0

NC

SER/BYTE

SCK/CLK

CS

SO

GNDP

NC

GND

RDY/BUSY

SI

VCCP

I/O7

VCC

WP

RESET

NC

I/O6

I/O5

I/O4

I/O3

NC

Rev. 3447A–DFLSH–2/04

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