AT45CS1282_14 datasheet(3/33 Pages) ATMEL

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AT45CS1282 [Preliminary]

3447A–DFLSH–2/04

Memory Architecture

Diagram

Device Operation

The device operation is controlled by instructions from the host processor. The list of

instructions and their associated opcodes are contained in Tables 1 through 4. A valid

instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode

and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main

memory address location through either the SI (serial input) pin or the 8-bit input pins

(I/O7 - I/O0). All instructions, addresses, and data are transferred with the most signifi-

cant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to

denote the 11 address bits required to designate a byte address within a buffer. Main

memory addressing is referenced using the terminology PA13 - PA0 and BA10 - BA0,

where PA13 - PA0 denotes the 14 address bits required to designate a page address

and BA10 - BA0 denotes the 11 address bits required to designate a byte address within

the page.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from

either one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8

protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing”

diagrams in this datasheet for details on the clock cycle sequences for each mode.

CONTINUOUS ARRAY READ: By supplying an initial starting address for the main

memory array, the Continuous Array Read command can be utilized to sequentially

read a continuous stream of data from the device by simply providing a clock signal; no

additional addressing information or control signals need to be provided. The DataFlash

incorporates an internal address counter that will automatically increment on every clock

cycle, allowing one continuous read operation without the need of additional address

sequences. To perform a continuous read, an opcode of E8H must be clocked into the

device followed by four address bytes (which comprises 7 don’t care bits plus the 25-bit

page and byte address sequence) and a series of don’t care clock cycles (24 if using the

serial interface or 19 if using the 8-bit interface). The first 14 bits (PA13 - PA0) of the

SECTOR 0a = 8 Pages

8,448 bytes (8K + 256)

SECTOR 0b = 248 Pages

261,888 bytes (248K + 7,936)

8 Pages

Page = 1,056 bytes

(1K + 32)

PAGE 0

PAGE 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 16,382

PAGE 16,383

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

SECTOR ARCHITECTURE

PAGE ARCHITECTURE

SECTOR 63 = 256 Pages

270,336 bytes (256K + 8K)

SECTOR 1 = 256 Pages

270,336 bytes (256K + 8K)

SECTOR 62 = 256 Pages

270,336 bytes (256K + 8K)

SECTOR 2 = 256 Pages

270,336 bytes (256K + 8K)

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