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AN4231 Datasheet(PDF) 7 Page - STMicroelectronics |
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AN4231 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 22 page ![]() DocID024130 Rev 2 7/22 AN4231 Low Power Modes overview Wakeup unit (WKPU) 8 KB of RAM Real time clock/ Autonomous Periodic Interrupt (RTC_API) CANSampler Slow IRC Fast IRC (can be optionally disabled) System Status and Configuration Module (SSCM) This mode is intended as follows: As an extreme low-power mode with everything powered down apart from the necessary circuitry to allow device wakeup and eventually a RTC/API (real time clock) implementation To be used by software to remain in the lowest power consumption state with no requirement to wake up quickly To exit from this mode, a wakeup event occurs. For this reason, the wake up unit is configured before entering in the STANDBY mode.However, in addition to booting from the default location, the microcontroller is also configured to boot from the backup RAM. In the case of booting from backup RAM, it is also possible to keep the CFLASH and DFLASH disable by writing “01” to the CFLAON and DFLAON field in the ME_DRUN_MC register prior to STANDBY entry. This allows a lower power consumption and a faster wakeup time, due to the fact that it does not need to wait for FLASH initialization (about ~120 us). If there is a STANDBY mode request while any wakeup event is active, the microcontroller does not enter STANDBY mode. In STANDBY mode power domain 1 is disabled. Power domains 2 and 3 are selectively configured to enable additional SRAM as defined in Figure 2. For more information on the Low Power Management refer to the Chapter 11 of the RM. 1.1 Settings for RAM in STANDBY STANDBY mode offers maximum power saving. The level of power saving is software- controllable via the settings in the PCU_PCONFn registers for power domain 2 onwards. Power domain 0 stays connected to the power supply while power domain 1 is disconnected from the power supply. Power domains 2 and 3 contain the backup RAM extensions and is only powered down during STANDBY mode. Therefore, writing ‘0’ to the respective bits for the other modes do not power down those domains. Depending on PCONF[2-3] configuration, there are four possible combinations for the amount of RAM active in STANDBY mode as shown in the Table 2. The 40 KB option results in a non-contiguous address space. |
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