September 2013

DocID024130 Rev 2

1/22

AN4231

Application note

Standby mode exit from FLASH to RAM configuration settings

for SPC564Bxx and SPC56ECxx device family

Introduction

The aim of this application note is to describe the correct procedure to manage one of the

available low power modes for the SPC564Bxx and SPC56ECxx devices; in particular the

enter/exit sequence for the STANDBY mode, which mode allows to reach the maximum

power saving state. Due to the multicore nature of the device, several combinations are

allowed.

In fact it is possible to exit from STANDBY mode enabling Z4 or Z0 core and using backup

RAM or FLASH memory.

Following the four possible combinations:

 From Z4 STANDBY exit enabling the Z4 core using Flash memory allocated for Z4

 From Z4 STANDBY exit enabling the Z4 core using the backup RAM allocated for Z4

 From Z4 STANDBY exit enabling the Z0 core using the Flash memory allocated for Z0

 From Z4 STANDBY exit enabling the Z0 core using the backup RAM allocated for Z0

All these combinations are obtained by easily modifyng the next example code. The Reset

Generation Module (RGM) contains the functionality to select the alternative boot via the

backup RAM on STANDBY mode exit.

This document describes about the STANDBY exit from Flash to RAM, using Z4 core

because it is the lowest power mode that are enabled with a low latency for wakeup event.

The CFLASH and DFLASH are kept in low power mode or in power down at the STANDBY

exit, then the PHASE2 and PHASE3 states of the reset state machine do not need to wait

for Flash initialization and all the processes are performed faster.

www.st.com