8

LTC1283

S

APPLICATI

I FOR ATIO

The LTC1283 is a 3V data acquisition component which

contains the following functional blocks:

1. 10-bit successive approximation capacitive

A/D converter

2. Analog multiplexer (MUX)

3. Sample-and-hold (S&H)

4. Synchronous, full duplex serial interface

5. Control and timing logic

DIGITAL CONSIDERATIONS

1. Serial Interface

The LTC1283 communicates with microprocessors and

other external circuitry via a synchronous, full duplex, 4-

wire serial interface (see Operating Sequence). The shift

clock (SCLK) synchronizes the data transfer with each bit

being transmitted on the falling SCLK edge and captured

on the rising SCLK edge in both transmitting and receiving

systems. The data is transmitted and received simulta-

neously (full duplex).

Data transfer is initiated by a falling chip select (CS) signal.

After the falling CS is recognized, an 8-bit input word is

for the next conversion. Simultaneously, the result of the

of the data exchange the requested conversion begins

sion is complete and the results will be available on the

next data transfer cycle. As shown below, the result of

a conversion is delayed by one CS cycle from the input

word requesting it.

2. Input Data Word

input on the first eight rising SCLK edges after chip select

ignored until the next CS cycle. The eight bits of the input

word are defined as follows:

DATA

TRANSFER

DATA

TRANSFER

A/D

CONVERSION

A/D

CONVERSION

LTC1283 • AI02

Operating Sequence

(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)

SGL/

DIFF

SELECT

1

SELECT

0

UNI

MSBF

WL1

MUX ADDRESS

MSB-FIRST/

LSB-FIRST

UNIPOLAR/

BIPOLAR

WORD

LENGTH

LTC1283 • AI03

ODD/

SIGN

WL0

1

2

3

45

67

8

9

10

B9

(SB)

B8

B7

B6

B5

B4

B3

B2

B1

B0

SCLK

DIN

DOUT

CS

LTC1283 • AI01

SGL/

DIFF

ODD/

SIGN

tCONV

tSMPL

tCYC

DON’T CARE

DON’T CARE

SEL

1

SEL

0

UNI

MSBF

WL1

WL0

SHIFT CONFIGURATION

WORD IN

SHIFT A/D RESULT OUT AND

NEW CONFIGURATION WORD IN