LTC1283CS datasheet(18/24 Pages) LINER

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LTC1283

APPLICATI

I FOR ATIO

Figure 10. “+” and “–” Input Settling Windows

“+” Input Settling

This input capacitor is switched onto the “+” input during

the sample phase (tSMPL, see Figure 10). The sample

phase starts at the 4th SCLK cycle and lasts until the falling

edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK

cycle depending on the selected word length). The voltage

on the “+” input must settle completely within this sample

time. Minimizing RSOURCE+ and C1 will improve the input

settling time. If large “+” input source resistance must be

used, the sample time can be increased by using a slower

SCLK frequency or selecting a longer word length. With

the minimum possible sample time of 8

µs, RSOURCE+ < 2k

and C1 < 20pF will provide adequate settling.

“–” Input Settling

At the end of the sample phase the input capacitor switches

to the “–” input and the conversion starts (see Figure 10).

During the conversion, the “+” input voltage is effectively

“held” by the sample-and-hold and will not affect the

conversion result. However, it is critical that the “–” input

voltage be free of noise and settle completely during the

first four ACLK cycles of the conversion time. Minimizing

RSOURCE– and C2 will improve settling time. If large “–”

input source resistance must be used, the time allowed for

settling can be extended by using a slower ACLK fre-

quency. At the maximum ACLK rate of 1MHz, RSOURCE–

< 1k and C2 < 20pF will provide adequate settling.

HORIZONTAL: 1

µs/DIV

Figure 11. Adequate Settling of Op Amp Driving Analog Input

Input Op Amps

When driving the analog inputs with an op amp it is

important that the op amp settle within the allowed time

(see Figure 10). Again, the “+” and “–” input sampling

times can be extended as described above to accommo-

date slower op amps. Most op amps including the LT1006

and LT1013 single supply op amps can be made to settle

well even with the minimum settling windows of 8

µs (“+”

input) and 4

µs (“–” input) which occur at the maximum

clock rates (ACLK = 1MHz and SCLK = 0.5MHz). Figures 11

and 12 show examples of adequate and poor op amp

settling.

SCLK

“+” INPUT

ACLK

LTC1283 • F10

234

• • •

MUX ADDRESS

SHIFTED IN

tSMPL

LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)

234

1ST BIT TEST

“–” INPUT MUST SETTLE

DURING THIS TIME

SAMPLE

HOLD

“+” INPUT

MUST SETTLE

DURING THIS TIME

“–” INPUT

• • •

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