LTC1283CS datasheet(19/24 Pages) LINER

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LTC1283

APPLICATI

I FOR ATIO

leakage specification of 1

µA (at 125°C) flowing through a

source resistance of 1k will cause a voltage drop of 1mV

or 0.4LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see typical

curve of Input Channel Leakage Current vs Temperature).

Noise Coupling into Inputs

High source resistance input signals (>500

Ω) are more

sensitive to coupling from external sources. It is prefer-

able to use channels near the center of the package (i.e.,

CH2-CH7) for signals which have the highest output

resistance because they are essentially shielded by the

pins of the package ends (DGND and CH0). Grounding any

unused inputs (especially the end pin, CH0) will also

reduce outside coupling into high source resistances.

4. Sample-and-Hold

Single-Ended Inputs

The LTC1283 provides a built-in sample-and-hold (S&H)

function for all signals acquired in the single-ended mode

(COM pin grounded). This sample-and-hold allows the

LTC1283 to convert rapidly varying signals (see typical

curve of S&H Acquisition Time vs Source Resistance). The

input voltage is sampled during the tSMPL time as shown

in Figure 10. The sampling interval begins after the fourth

MUX address bit is shifted in and continues during the

remainder of the data transfer. On the falling edge of the

final SCLK, the S&H goes into hold mode and the conver-

sion begins. The voltage will be held on either the 8th,

10th, 12th or 16th falling edge of the SCLK depending on

the word length selected.

Differential Inputs

With differential inputs, or when the COM pin is not tied to

ground, the A/D no longer converts just a single voltage

but rather the difference between two voltages. In these

cases, the voltage on the selected “+” input is still sampled

and held and therefore may be rapidly time varying just as

in single-ended mode. However, the voltage on the se-

lected “–” input must remain constant and be free of noise

and ripple throughout the conversion time. Otherwise, the

HORIZONTAL: 1

µs/DIV

Figure 12. Poor Op Amp Settling Can Cause A/D Errors

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 13. For large values of CF (e.g., 1µF), the

capacitive input switching currents are averaged into a net

DC current. Therefore, a filter should be chosen with small

resistor and large capacitor to prevent DC drops across

the resistor. The magnitude of the DC current is approxi-

mately IDC = 65pF × VIN/tCYC and is roughly proportional

to VIN. When running at the minimum cycle time of 68µs,

the input current equals 2.5

µA at VIN = 2.5V. In this case,

a filter resistor of 100

Ω will cause 0.1LSB of full-scale

error. If a larger filter resistor must be used, errors can be

eliminated by increasing the cycle time as shown in the

typical curve Maximum Filter Resistor vs Cycle Time.

Input Leakage Current

Input leakage currents can also create errors if the source

resistance gets too large. For instance, the maximum input

RFILTER

VIN

CFILTER

LTC1283 • F13

LTC1283

“+”

“–”

IDC

Figure 13. RC Input Filtering

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