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LTC1283CS Datasheet(PDF) 13 Page - Linear Technology |
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LTC1283CS Datasheet(HTML) 13 Page - Linear Technology |
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13 / 24 page  13 LTC1283 S APPLICATI I FOR ATIO Figure 3. CS High During Conversion Figure 4. CS Low During Conversion Serial Port Microprocessors Most synchronous serial formats contain a shift clock (SCLK) and two data lines, one for transmitting and one for receiving. In most cases data bits are transmitted on the falling edge of the clock (SCLK) and captured on the rising edge. However, serial port formats vary among MPU manufacturers as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). They also vary as to the order in which the bits are transmitted (LSB- or MSB-first). The following examples show how the LTC1283 accommodates these differences. National MICROWIRE (COP820C) The COP820C transfers data MSB-first and in 8-bit incre- ments. This is easily accommodated by setting the LTC1283 to MSB-first format and 10-bit word length. The data output word is then received by the COP820C in one 8-bit block and one 2-bit block. Table 2. 3V Microprocessor with Hardware Serial Interfaces Compatible with the LTC1283* PART NUMBER TYPE OF INTERFACE Motorola MC68HC11 SPI MC68HC05 SPI RCA CDP68HC05 SPI National Semiconductor COP800 Family MICROWIRE/PLUS † HPC16000 Family MICROWIRE/PLUS † Texas Instruments TMS70C02 Serial Port TMS70C42 Serial Port *Contact factory for interface information for processors not on this list †MICROWIRE/PLUS is a trademark of National Semiconductor Corp. B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SHIFT RESULT OUT AND NEW ADDRESS IN SCLK CS DOUT DIN tSMPL SAMPLE ANALOG INPUT SHIFT MUX ADDRESS IN LTC1283 • F03 40 TO 44 ACLK CYCLES ODD/ SIGN SEL 1 SEL 0 UNI MSBF WL1 WL0 DON’T CARE SGL/ DIFF ODD/ SIGN SEL 1 SEL 0 UNI MSBF WL1 WL0 SGL/ DIFF B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SHIFT RESULT OUT AND NEW ADDRESS IN SCLK CS DOUT DIN tSMPL SAMPLE ANALOG INPUT SHIFT MUX ADDRESS IN LTC1283 • F04 40 TO 44 ACLK CYCLES ODD/ SIGN SEL 1 SEL 0 UNI MSBF WL1 WL0 DON’T CARE SGL/ DIFF ODD/ SIGN SEL 1 SEL 0 UNI MSBF WL1 WL0 SGL/ DIFF SCLK MUST REMAIN LOW |
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