NCN5130 datasheet(9/58 Pages) ONSEMI

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NCN5130

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Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol

Unit

Max

Typ

Min

Remark/Test Conditions

Parameter

Pin(s)

FAN−IN CONTROL

Ipu,fanin

FANIN

Pull−Up Current FANIN−pin

FANIN shorted to GND,

Pull−up connected to VAUX

DIGITAL INPUTS

VIL

SCK/UC2,

SDI/RXD,

CSB/UC1,

TREQ,

MODE1,

MODE2,

XSEL,

XCLKC,

XTAL2

Logic Low Threshold

0.7

VIH

Logic High Threshold

2.65

VDDD

RDOWN

Internal Pull−Down Resistor

SCK/UC2−, SDI/RXD− and

CSB/UC1 pin excluded. Only valid

in Normal State.

DIGITAL OUTPUTS

VOL

SCK/UC2,

SDO/TXD,

CSB/UC1,

XCLK,TRIG

Logic low output level

0.4

VOH

Logic high output level

VDDD −

0.45

VDDD

SCK/UC2,

XCLK,TRIG

Load Current

SDO/TXD,

CSB/UC1

VOL

SAVEB,

RESETB

Logic low level open drain

IOL = 4 mA

0.4

Rup

Internal Pull−up Resistor

ANALOG OUTPUT

PVBUS

ANAOUT

Analog output division ratio for VBUS

0.067

0.071

0.075

PVFILT

Analog output division ratio for VFILT

0.071

0.075

0.079

PV20V

Analog output division ratio for V20V

0.086

0.091

0.096

PVDDA

Analog output division ratio for VDDA

0.438

0.462

0.485

PVDD2

Analog output division ratio for VDD2MV

0.950

1.000

1.050

PIBUS

Analog output conversion ratio for IBUS

14.0

20.9

28.8

V/A

PTJ

Analog output conversion ratio for Tjunction

−4

mV/K

VTJOFF

Analog output offset for Tjunction at 300K

1.309

VOFF

Analog output offset voltage

−12

tSW,ANA

Time between writing Analog Control Register 1 and stable ANAOUT

voltage (<1 nF capacitive load)

TEMPERATURE MONITOR

TTW

Thermal Warning

Rising temperature (See Figure 8)

105

115

125

°C

TTSD

Thermal shutdown

Rising temperature (See Figure 8)

130

140

150

°C

THyst

Thermal Hysteresis

See Figure 8

°C

Delta TTSD and TTW

See Figure 8

21.7

°C

PACKAGE THERMAL RESISTANCE VALUE

Rq,ja

Thermal Resistance

Junction−to−Ambient

Simulated Conform

JEDEC JESD−51, (2S2P)

K/W

Simulated Conform

JEDEC JESD−51, (1S0P)

K/W

Rq,jp

Thermal Resistance

Junction−to−Exposed Pad

0.95

K/W

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