LTC4240IGN datasheet(8/28 Pages) LINER

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LTC4240

4240f

PWRGD (Pin 8): Open-Drain Power Good Output. Con-

nect the CPCI HEALTHY# signal to the PWRGD pin.

PWRGD remains low while V12VOUT ≥ 11.1V, V3VOUT ≥

2.9V, V5VOUT ≥ 4.65V and VEEOUT ≤ –10.5V. When any of

the supplies drops below its power good threshold volt-

age, PWRGD will go high after a 10

µsdeglitchingtime.The

switches will not be turned off when PWRGD goes high,

unless a fault has occurred. The CPCI specification calls

for a 0.01

µF bypass capacitor on the backplane for

HEALTHY#.

BE (Pin 9): QuickSwitch Bus Enable Output. The BE output

remains high until power is good on all supplies. This

serves to isolate the I/O data lines during live

insertion. This is a CMOS output powered by 5VIN.

GND (Pin 10): Analog Ground. Connect to analog ground

plane.

ADDRIN (Pin 11): I2C Address Programming Input. The

I2C address is programmed by connecting the ADDRIN

pin to a resistor divider between the 5VIN pin and GND. See

Table 1 for 1% resistor values and corresponding ad-

dresses. Resistors must be placed close to the ADDRIN

pin to minimize errors due to stray capacitance and

resistance on the board trace. Connect this pin to ground

if I2C is not used.

SDA (Pin 12): I2C Data Input and Output. Note that TTL

levels are used. Connect this pin to ground if I2C is not

used.

SCL (Pin 13): I2C Clock Input, 100kHz Maximum. Note

that TTL levels are used. Do not float. Connect this pin to

ground if I2C is not used.

RESETOUT (Pin 14): Open-Drain Reset Output. Connect

the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.

RESETOUT is the logical combination of RESETIN, PWRGD,

and I2C RESETOUT latch output.

LED (Pin 15): CPCI Status LED. Pulls low to light LED

when RESETOUT is low or when the I2C LED latch is set.

DGND (Pin 16): Digital Ground. Connect to ground plane.

DRIVE (Pin 17): External transistor’s base drive output for

bus precharge. Connects to the base of an external NPN

emitter-follower which in turn biases the PRECHARGE

PRSNT1# (Pin 1): PCI Present Detect Input 1. PRSNT1#

and PRSNT2# are readable over the I2C Bus. PRSNT1#

and PRSNT2# indicate the maximum power used by the

card. Do not float.

PRSNT2# (Pin 2): PCI Present Detect Input 2. Do not float.

12VIN (Pin 3): 12V Supply Input. A 0.5Ω switch is inter-

nally connected between 12VIN and 12VOUT with foldback

current limit. An undervoltage lockout circuit prevents the

switches from turning on while the 12VIN pin is below 8V.

12VIN provides power to some of the LTC4240’s internal

circuitry. See Input Transient Protection section on how to

protect 12VIN from large voltage transients.

VEEIN (Pin 4): –12V Supply Input. A 1Ω internal switch is

connected between VEEIN and VEEOUT with foldback cur-

rent limit. An undervoltage lockout circuit prevents the

switches from turning on while VEEIN is above –9V. See

Connecting VEEIN section for more notes on VEEIN and

VEEOUT. Also refer to Input Transient Protection section.

TIMER/AUX 12VIN (Pin 5): Current Fault Inhibit Timing

Input. Connect a capacitor from TIMER to GND. With the

LTC4240 turned off (OFF/ON = HIGH), the TIMER pin is

internally held at GND. When the device is turned on, an

11.5

µA pull-up current source is connected to TIMER.

Current limit faults will be ignored until the voltage at the

TIMER pin rises above 5.5V. The Timer capacitor also

serves as an auxiliary charge reservoir for internal VCC in

the event the 12VIN pin voltage glitches below the LTC4240

UVL threshold voltage.

5VOUT (Pin 6): 5V Output Sense. The PWRGD pin will not

pull low until the 5VOUT pin voltage exceeds 4.65V. When

the power switches are turned off, a 50

Ω resistor pulls

5VOUT to ground.

FAULT (Pin 7): Open-Drain Fault Output . FAULT is pulled

low when a current limit fault is detected. Current limit

faults are ignored until the voltage at the TIMER pin is

above 5.5V. Once the TIMER cycle is complete, FAULT

pulls low and the LTC4240 turns off (in the event of an

overcurrent fault lasting longer than 35

µs). The LTC4240

will remain in the off state until the OFF/ON pin is cycled

high then low or power is cycled. Note that the OFF/ON

cycling can also be performed using I2C bus.

PI FU CTIO S

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