LTC4240IGN datasheet(9/28 Pages) LINER

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LTC4240

4240f

long pin must be connected to 3VIN to ensure precharge

output. See Input Transient Protection section.

3VSENSE (Pin 23): 3.3V Current Limit Sense. A sense

resistor placed between 3VIN and 3VSENSE determines the

current limit for this supply. A foldback feature makes the

current limit decrease as the voltage at the 3VOUT pin

approaches 0V. To disable current limit, 3VSENSE and 3VIN

must be tied together.

3VOUT (Pin 24): 3.3V Output Sense. The PWRGD pin

cannot pull low until the 3VOUT pin voltage exceeds 2.9V.

If no 3.3V input supply is available, tie the 3VOUT pin to the

5VOUT pin. When the power switches are turned off, a

150

Ω resistor pulls 3VOUT to ground.

VEEOUT (Pin 25): –12V Supply Output. An internal 1Ω

switch is connected between VEEIN and VEEOUT. VEEOUT

must exceed –10.5V before the PWRGD pin pulls low.

When the power switches are turned off, a 650

Ω resistor

pulls VEEOUT to ground.

12VOUT (Pin 26): 12V Supply Output. A 0.5Ω switch is

connected between 12VIN and 12VOUT. 12VOUT must

exceed 11.1V before the PWRGD pin can pull low. When

the power switches are turned off, a 430

Ω resistor pulls

12VOUT to ground.

RESETIN (Pin 27): PCI Reset Input. Connect the CPCI

PCI_RST# signal to the RESETIN pin. Pulling RESETIN low

will cause RESETOUT to pull low. Note that the I2C

RESETIN latch output can also set RESETOUT. Do not

float.

OFF/ON (Pin 28): OFF/ON Input. Connect the CPCI

BD_SEL# signal to the OFF/ON pin. When the OFF/ON pin

is pulled low, the GATE pin is pulled high by a 65

µA current

source and the internal 12V and –12V switches are turned

on. When the OFF/ON pin is pulled high, the GATE pin will

be pulled to ground by a 200

µAcurrentsourceandthe12V

and –12V switches turn off.

Cycling the OFF/ON pin high and low will reset a tripped

circuit breaker and start a new power-up sequence. The

I2C OFF/ON latch output can also be used to reset the

electronic circuit breaker. Do not float.

node. An external 1k resistor between the transistor’s base

and 3VIN is needed.

PRECHARGE (Pin 18): Precharge Monitor Input. An inter-

nal error amplifier servos the DRIVE pin voltage to keep the

precharge node at 1V. Becomes valid when long 5V and

3.3V power pins make contact .Tie pins 17 and 18 together

if precharge function is unused.

GATE (Pin 19): High Side Gate Drive for the External 3.3V

and 5V N-Channel Power Transistors. An external series

RC network is required for the current limit loop compen-

sation and to set the maximum ramp-up rate. During

power-up, the slope of the voltage rise at the GATE pin is

set by the 65

µA current source charging the external GATE

capacitor or by the 3.3V or 5V current limit and the

associated output capacitor. During power-down, a 200

µA

current source pulls the GATE pin to GND.

The voltage at the GATE pin will be modulated to maintain

a constant current when either the 3.3V or 5V supply goes

into current limit and the TIMER pin is less than 5.5V. Once

the TIMER pin is above 5.5V, and in the event of a current

fault condition lasting for longer than 35

µs, the GATE pin

is immediately pulled to GND.

5VSENSE (Pin 20): 5V Current Limit Sense. A sense resistor

placed between 5VIN and 5VSENSE determines the current

limit for this supply. A foldback current feature makes the

current limit decrease as the voltage at the 5VOUT pin

approaches 0V. To disable the current limit, 5VSENSE and

5VIN must be tied together.

5VIN (Pin 21): 5V Supply Sense Input. An undervoltage

lockout circuit prevents the switches from turning on

when the voltage at the 5VIN pin is less than 4.3V. At least

one long pin must be connected to 5VINtoensureprecharge

output. See Input Transient Protection section.

3VIN (Pin 22): 3.3V Supply Sense Input. An undervoltage

lockout circuit prevents the switches from turning on

when the voltage at the 3VIN pin is less than 2.45V. If no

3.3V input supply is available, connect two series diodes

between 5VIN and 3VIN (tie anode of first diode to 5VIN and

cathode of second diode to 3VIN, Figure 15). At least one

PI FU CTIO S

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