TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

20

POST OFFICE BOX 655303

ARBCLK switching characteristics over recommended operating free-air temperature range (see

Figure 14)

TEST CONDITIONS

MIN

MAX

UNIT

tc4

Cycle time, internal arbitration clock ( ARBCLKI

ARBPGM)

VCC = 3.3 V,

See Note 11

26

Note 14

ns

tc4

Cycle time, internal arbitration clock ( ARBCLKI

÷ ARBPGM)

VCC = 5 V

14

Note 14

ns

tc5

Cycle time, arbitration clock

VCC = 3.3 V,

See Note 11

26

ns

tc5

Cycle time, arbitration clock

VCC = 5 V

14

ns

td42

Delay time, ARBCLKI

↑ to ARBCLK0↑ ( 1)

VCC = 3.3 V,

See Note 11

13

ns

td42

Delay time, ARBCLKI

↑ to ARBCLK0↑ (

÷1)

VCC = 5 V

7.3

ns

td43

Delay time, ARBCLKI

↓ to ARBCLK0↓ ( 1)

VCC = 3.3 V,

See Note 11

15.5

ns

td43

Delay time, ARBCLKI

↓ to ARBCLK0↓ (

÷1)

VCC = 5 V

10

ns

td44

Delay time, ARBCLKI

↑ to ARBCLK0↑ ( 2)

VCC = 3.3 V,

See Note 11

15.3

ns

td44

Delay time, ARBCLKI

↑ to ARBCLK0↑ (

÷2)

VCC = 5 V

8.8

ns

td45

Delay time, ARBCLKI

↑ to ARBCLK0↓ ( 2)

VCC = 3.3 V,

See Note 11

17.5

ns

td45

Delay time, ARBCLKI

↑ to ARBCLK0↓ (

÷2)

VCC = 5 V

11

ns

td46

Delay time, ARBCLKI

↑ to ARBCLK0↑ ( 4)

VCC = 3.3 V,

See Note 11

19.5

ns

td46

Delay time, ARBCLKI

↑ to ARBCLK0↑ (

÷4)

VCC = 5 V

11.5

ns

td47

Delay time, ARBCLKI

↑ to ARBCLK0↓ ( 4)

VCC = 3.3 V,

See Note 11

21.5

ns

td47

Delay time, ARBCLKI

↑ to ARBCLK0↓ (

÷4)

VCC = 5 V

13.5

ns

td48

Delay time, ARBCLKI

↑ to ARBCLK0↑ ( 8)

VCC = 3.3 V,

See Note 11

22.7

ns

td48

Delay time, ARBCLKI

↑ to ARBCLK0↑ (

÷8)

VCC = 5 V

13.5

ns

td49

Delay time, ARBCLKI

↑ to ARBCLK0↓ (

÷8)

VCC = 3.3 V,

See Note 11

25

ns

td49

Delay time, ARBCLKI

↑ to ARBCLK0↓ (

÷8)

VCC = 5 V

15.7

ns

NOTES: 11. TL16PC564BLVI device tested at 3 V.

14. tc4 MAX = N/6, where N = shortest (in ns) of the two attribute-memory accesses, host CPU or subsystem.

reset timing requirements over recommended ranges of operating free-air temperature and supply

voltage (unless otherwise noted) (see Figure 15)

TEST CONDITIONS

MIN

MAX

UNIT

tw22

Pulse duration, RESET active

8

⋅tc5

ns

tw23

Pulse duration, RESET inactive

8

⋅tc5

ns

td50

Delay time, ARBCLKI

↑ to RST low

VCC = 3.3 V,

See Note 11

10.4

ns

td50

Delay time, ARBCLKI

↑ to RST low

VCC = 5 V

7.5

ns

td51

Delay time, ARBCLKI

↑ to RST high impedance

VCC = 3.3 V,

See Note 11

13.9

ns

td51

Delay time, ARBCLKI

↑ to RST high impedance

VCC = 5 V

9.7

ns

NOTE 11: TL16PC564BLVI device tested at 3 V.

subsystem interrupt-request timing requirements over recommended ranges of operating free-air

temperature and supply voltage (see Figure 16)

MIN

MAX

UNIT

td52

Delay time, WE

↑ to IRQ↑ (see Note 15)

2tc5

3tc5

ARBCLKI

cycles

td53

Delay time, SCR bit 6

↑ to IRQ↓ (see Note 16)

tc5

2tc5

ARBCLKI

cycles

NOTES: 11. TL16PC564BLVI device tested at 3 V.

15. Synchronized to rising edge of ARBCLKI

16. Synchronized to falling edge of ARBCLKI

Not Recommended For New Designs