TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

26

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

HA(9 − 0)

CE1, CE2

tc2

th9

Data Input Established

HD(7 − 0)

tsu12

See Note C

tsu10

WE

tsu8

trec1

See Note B

See Note A

See Note A

90%

10%

90%

10%

90%

10%

90%

90%

10%

90%

10%

90%

10%

10%

NOTES: A. The hatched portion may be either high (H) or low (L).

B. OE must be high (H).

C. When the data I/O terminal is in the output state, no signals should be applied to HD(7 − 0) by the system.

Figure 8. Host CPU Attribute-Memory Write Timing Waveforms (CE Control)

Not Recommended For New Designs