TL16PC564BLVIPZ datasheet(4/35 Pages) TI1

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TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

INTER-

†

I/O

DESCRIPTION

NAME

PZ NO.

INTER-

FACE†

I/O

DESCRIPTION

ALE (AS)

Address-latch enable/address strobe. ALE(AS) is an address-latch enable in the Intel mode

and an address strobe in the Zilog mode. ALE (AS) is active high for an Intel subsystem and

active low for a Zilog subsystem.

ARBCLKO

Arbitration clock output. ARBCLKO is equal to the input on ARBCLKI divided by the

binary-coded divisor input on ARBPGM (1 − 0).

ARBCLKI

Arbitration clock input. ARBCLKI is the base clock used in arbitration for the attribute memory

DRAM and the reset validation circuitry.

ARBPGM0

ARBPGM1

Arbitration clock divisor program. These two bits set the divisor for ARBCLKI. Divide by 1, 2,

4, and 8 are available.

BAUDOUT

Baud output. BAUDOUT is an active-low 16

× signal for the transmitter section of the UART.

The clock rate is established by the reference clock (UARTCLK) frequency divided by a divisor

specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver

section by tying this output to the RCLK input.

CE1

CE2

Card enable 1 and card enable 2 are active-low signals. CE1 enables even-numbered

address bytes, and CE2 enables odd-numbered address bytes. A multiplexing scheme based

on HA0, CE1, and CE2 allows an 8-bit host to access all data on HD0 through HD7 if desired.

These signals have internal pullup resistors.

Chip select. CS is the active-low chip select from the Zilog or Intel microcontroller.

CTS

Clear to send. CTS is an active-low modem status signal whose condition can be checked by

reading bit 4 (CTS) of the modem status register (MSR). Bit 0 (delta clear to send) of the MSR

indicates that the signal has changed states since the last read from the MSR. If the

modem-status interrupt is enabled when CTS changes states, an interrupt is generated.

DCD

Data carrier detect. DCD is an active-low modem-status signal whose condition can be

checked by reading bit 7 (DCD) of the MSR. Bit 3 (delta data carrier detect) of the MSR

indicates that the signal has changed states since the last read from the MSR. If the

modem-status interrupt is enabled when DCD changes states, an interrupt is generated.

DSR

Data set ready. DSR is an active-low modem status signal whose condition can be checked

by reading bit 5 (DSR) of the MSR. Bit 1 (delta data set ready) of the MSR indicates that the

signal has changed states since the last read from the MSR. If the modem-status interrupt is

enabled when DSR changes states, an interrupt is generated.

DTR

Data terminal ready. DSD is an active-low signal. When active, DTR informs the modem or

data set that the UART is ready to establish communication. DTR is placed in the active state

by setting the DTR bit 0 of the modem control register (MCR) to a high level. DTR is placed

in the inactive state either as a result of a reset, doing a loop-mode operation, or resetting bit

0 (DTR) of the MCR.

EXTEND

FIFO extend. When EXTEND is high, the UART is configured as a standard TL16C550 with

16-byte transmit and receive FIFOs. When EXTEND is low and FIFO control register (FCR)

bit 5 is high, the FIFOs are extended to 64 bytes and the receiver-interrupt trigger levels adjust

accordingly. EXTEND low in conjunction with FIFO control register (FCR) bit 4 set high

enables the auto-RTS function.

GND

4, 6, 13,16,30,

39,41, 43, 54,

66, 68, 69,80, 91

Common ground

† Host = H, Subsystem = S, UART = U, Miscellaneous = M

Not Recommended For New Designs

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