PC87591L datasheet(60/437 Pages) NSC

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2.0 Signal/Pin Description and Configuration (Continued)

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Revision 1.07

Input to Output Echo Enable Register 1 and 2 (IOEE1 and IOEE2)

The IOEE1 and IOEE2 registers are read/write, byte-wide registers. They enable the echoing of some of the General-Pur-

pose Input ports, equipped with wake-up, to a specified output. The IOEE bits have an impact only when the output GPIO

is configured to its GPIO function. IOEE1 and IOEE2 are cleared (0016) on reset.

The format of IOEE1 is:

IOEE1 Location: 00 FF0216

Type: R/W

Table 9. GPIO Echo Functions Routing and Echo Enable Bit Assignments

Output Port

Echo Enable Bit

Input Port

IOPA0

EEPA0 bit in IOEE1 register

IOPC4/EXWINT22

IOPA1

EEPA1 bit in IOEE1 register

IOPE6/LPCPD/EXWINT45

IOPA2

EEPA2 bit in IOEE1 register

IOPE7/CLKRUN/EXWINT46

IOPA3

EEPA3 bit in IOEE1 register

IOPF6/PSCLK4

IOPA4

EEPA4 bit in IOEE1 register

IOPF7/PSDAT4

IOPC0

EEPC0 bit in IOEE2 register

IOPE4/SWIN

IOPB0

EEPB0 bit in IOEE2 register

IOPD0/EXWINT20

IOPB1

EEPB1 bit in IOEE2 register

IOPD1/EXWINT21

IOPB2

EEPB2 bit in IOEE2 register

IOPC6/EXWINT23

IOPD3

EEPD3 bit in IOEE2 register

IOPD2/EXWINT24

Bit

76543210

Name

Reserved

EEPA4

EEPA3

EEPA2

EEPA1

EEPA0

Reset

00000000

Bit

Description

EEPA0.

0: Echo Disabled

1: Echo Enabled

EEPA1.

0: Echo Disabled

1: Echo Enabled

EEPA2.

0: Echo Disabled

1: Echo Enabled

EEPA3.

0: Echo Disabled

1: Echo Enabled

EEPA4.

0: Echo Disabled

1: Echo Enabled

7-5

Reserved.

PC87591L Datasheet(PDF) 60 Page - National Semiconductor (TI)

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