LR745 datasheet(7/15 Pages) MICROCHIP

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DS20005394A-page 7

LR745

3.4

Block Diagram

FIGURE 3-3:

BLOCK DIAGRAM

LR745 is a high voltage, switch-mode power supply

start-up circuit which has 3 terminals: VIN, GND, and

VOUT. An input voltage range of 35 - 450V DC can be

applied directly at the input VIN pin. The output voltage,

VOUT, is monitored by the 2 comparators: comp1 and

comp2. An internal reference, VREF, and resistor

divider R1, R2, and R3set the nominal VOUT trip points

of 7.0V for comp1 and 13.25V for comp2.

When a voltage is applied on VIN, VOUT will start to

ramp up from 0V. When VOUT is less than 7.0V, the out-

put of comp1 will be at a logic high state, keeping the D

flip-flop in a reset state. The output of the D flip-flop, Q,

will be at logic low keeping transistor M2 off. The data

input for the D flip-flop, D, is internally connected to a

logic high. As VOUT becomes greater than 7.0V, comp1

will change to a logic low state. VOUT will continue to

increase, and the constant current source, typically

3.0mA output, will charge an external storage capaci-

tor. As VOUT reaches above 13.25V, the output of

comp2 will then switch from a logic high to a logic low

state. The D flip-flop’s output does not change state

since its clock input is designed to trigger only on a ris-

ing edge, logic low to logic high transition. When there

is no load connected to the output, the output voltage

will continue to increase until it reaches 21.5V, which is

the Zener voltage minus the threshold voltage of tran-

sistor M1. The Zener voltage is typically 23V, and the

threshold voltage of M1 is typically 1.5V. The Zener

diode is biased by resistor R4.

VOUT will start to decrease when it is connected to an

external load greater than the internal constant current

source, which is the case when the PWM IC starts up.

When VOUT falls below 13.25V, the output of comp2 will

switch from a logic low to a logic high. The output of

comp2 will clock in a logic 1 into the D flip-flop, causing

the D flip-flop’s output, Q, to switch from a logic low to

a logic high. Transistor M2 will then be turned on pulling

the gate of transistor M1 to ground, thereby turning

transistor M1 off. Transistor M1 will remain off as long

as VOUT is greater than 7.0V. Once VOUT decreases

below 7.0V, comp1 will reset the D flip-flop, thereby

turning transistor M2 off and transistor M1 back on.

CLK

Clock

GND

R D

OUT

VOUT

VIN

2.0 - 4.0mA

23V

REF

Reset

comp1

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