CS8420 datasheet(21/80 Pages) CIRRUS

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CS8420

DS245PP2

OMCK OUT ON RMCK

A special mode is available that allows the clock

that is being input through the OMCK pin to be out-

put through the RMCK pin. This feature is con-

trolled by the SWCLK bit in register 4 of the

control registers. When the PLL loses lock the fre-

quency of the VCO drops to 300 kHz. The SWCLK

function allows the clock from RMCK to be used

as a clock in the system without any disruption

when input is removed from the Receiver.

PLL EXTERNAL COMPONENTS

The PLL behavior is affected by the external filter

component values. Figure 5 shows the configura-

tion of the required 2 capacitors and 1 resistor. Two

alternate sets of component values are recommend-

ed, depending on the requirements of the applica-

tion (see Table 1). The default set, called “fast”,

accommodates input sample rates of 16 kHz to

108 Hz with no component changes. It has the

highest corner frequency jitter attenuation curve,

and takes the shortest time to lock. The alternate

component set, called “medium” allows the lowest

input sample rate to be 8 kHz, and increases the

lock time of the PLL. Lock times are worst case for

an Fsi transition of 96 kHz.

9.1

Error Reporting and Hold Function

While decoding the incoming AES3 data stream,

the CS8420 can identify several kinds of error, in-

dicated in the Receiver Error register. The UN-

LOCK bit indicates whether the PLL is locked to

the incoming AES3 data. The V bit reflects the cur-

rent validity bit status. The CONF (confidence) bit

indicates the amplitude of the eye pattern opening,

indicating a link that is close to generating errors.

The BIP (bi-phase) error bit indicates an error in in-

coming bi-phase coding. The PAR (parity) bit indi-

cates a received parity error.

The error bits are “sticky”: they are set on the first

occurrence of the associated error, and will remain

set until the user reads the register via the control

port. This enables the register to log all unmasked

errors that occurred since the last time the register

was read.

The Receiver Error Mask register allows masking

of individual errors. The bits in this register serve

as masks for the corresponding bits of the Receiver

Error Register. If a mask bit is set to 1, the error is

considered unmasked, meaning that its occurrence

will be reported in the receiver error register, will

affect the RERR pin, will invoke the occurrence of

a RERR interrupt, and will affect the current audio

sample according to the status of the HOLD bits.

The HOLD bits allow a choice of holding the pre-

vious sample, replacing the current sample with

zero (mute), or do not change the current audio

sample. If a mask bit is set to 0, the error is consid-

ered masked, meaning that its occurrence will not

be reported in the receiver error register, will not

induce a pulse on RERR or generate a RERR inter-

rupt, and will not affect the current audio sample.

The QCRC and CCRC errors do not affect the cur-

rent audio sample, even if unmasked.

9.2

Channel Status Data Handling

The first 2 bytes of the Channel Status block are de-

coded into the Receiver Channel Status register.

The setting of the CHS bit in the Channel Status

Data Buffer Control register determines whether

Type

RFILT (k

Ω)CFILT (µF)

CRIP (nF)

Fsi Range (kHz)

PLL Lock Time (ms)

Medium

0.909

1.8

8 to 96

Fast

1.78

0.47

8.2

16 to 108

Table 1. PLL External Component Values

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