CS8420 datasheet(47/80 Pages) CIRRUS

47 / 80 page

CS8420

DS245PP2

Overall Device Control:

H/S - Hardware or Software Control Mode Select *

The H/S pin determines the method of controlling the operation of the CS8420, and the method of

accessing CS and U data. In software mode, device control and CS and U data access is primarily via

the control port, using a microcontroller. In hardware mode, alternate modes and access to CS and U

data is provided by pins. This pin should be permanently tied to VD+ or DGND.

RST - Reset Input *

When RST is low, the CS8420 enters a low power mode and all internal states are reset. On initial

power up, RST must be held low until the power supply is stable, and all input clocks are stable in

frequency and phase. This is particularly true in hardware mode with multiple CS8420 devices, where

synchronization between devices is important.

INT - Interrupt Output

The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting

INT are maskable via control registers. The condition(s) that initiated interrupt are readable via a control

a control register. Once set true, the INT pin goes false only after the interrupt status registers have

been read, and the interrupt status bits have returned to zero.

Audio Input Interface:

SDIN - Serial Audio Input Port Data Input

Audio data serial input pin.

ISCLK - Serial Audio Input Port Bit Clock input or output

Serial bit clock for audio data on the SDIN pin.

ILRCK - Serial Audio Input Port Left/Right Clock input or output

Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)

AES3/SPDIF Receiver Interface:

RXP, RXN - Differential Line Receiver Inputs

Differential line receiver inputs, carrying AES3 type data.

RERR - Receiver Error Indicator

When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is

updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are:

validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock

in the PLL. Each condition may be optionally masked from affecting the RERR pin using the Receiver

Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon

as an unmasked error occurs and goes low immediately when all unmasked errors go away.

EMPH - Pre-emphasis Indicator Output

EMPH is low when the incoming AES3 data indicates the presence of 50/15

µs pre-emphasis. When

the AES3 data indicates the absence of pre-emphasis or the presence of other than 50/15

µs pre-

emphasis EMPH is high. This is also a start-up option pin, and requires a 47 k

Ω resistor to either VD+

or DGND, which determines the AD2 address bit for the control port in I2C mode.

Audio Output Interface:

SDOUT - Serial Audio Output Port Data Output

Audio data serial output pin.

CS8420 Datasheet(PDF) 47 Page - Cirrus Logic

CS8420 Datasheet(HTML) 47 Page - Cirrus Logic

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