WM9713 datasheet(27/111 Pages) WOLFSON

27 / 111 page

Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

11:9

DIV

010

Voice DAC clock to PCMCLK divider. In

master mode PCMCLK is derived from Voice

DAC clock.

000 : PCMCLK = Voice DAC clock

001 : PCMCLK = Voice DAC clock / 2

010 : PCMCLK = Voice DAC clock / 4

011 : PCMCLK = Voice DAC clock / 8

100 : PCMCLK = Voice DAC clock / 16

VDACOS

VXDAC oversample rate:

0: 128 x fs

1: 64 x fs

PCMCLK polarity

1 = invert PCMCLK polarity

0 = normal PCMCLK polarity

FSP

Right, Left and I

2S modes – PCMFS polarity

1 = invert PCMFS polarity

0 = normal PCMFS polarity

DSP Mode – mode A/B select

0 = MSB is available on 2nd PCMCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st PCMCLK rising

edge after LRC rising edge (mode B)

5:4

SEL

PCM ADC channel select

00 = Output left and right ADC data

01 = Swap and output left and right ADC data

10 = Output left ADC data only

11 = Output right ADC data only

3:2

PCM Data Word Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

1:0

FMT

PCM Data Format Select

11 = DSP Mode

10 = I

2S Format

01 = Left justified

00 = Right justified

Table 7 PCM Codec Control

Note: Right justified does not support 32-bit data.

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