PC87311AVF datasheet(38/78 Pages) NSC

38 / 78 page

40 FDC Command Set Description (Continued)

change in status of any disk drive Four possible causes of

the interrupt are

1 Upon entering the Result Phase of

Read Data command

Read Deleted Data command

Read a Track command

Read ID command

Write Data command

Write Deleted Data command

Format command

Scan command

Verify command

2 During data transfers in the Execution Phase while in the

Non-DMA mode

3 Ready Changed State during the polling mode for an in-

ternally selected drive (Occurs only after a hardware or

software reset)

4 Seek Relative Seek or Recalibrate termination

An interrupt due to reasons 1 and 2 does not require the

Sense Interrupt command and is cleared automatically This

interrupt occurs during normal command operations and is

easily discernible by the mP via the MSR This interrupt is

cleared reading or writing information fromto the Data Reg-

ister (FIFO)

Interrupts caused by reasons 3 and 4 are identified with the

aid of the Sense Interrupt command The interrupt is cleared

after the first result byte has been read Use bits 5 6 and 7

of ST0 to identify the cause of the interrupt as shown in

Table 4-11

TABLE 4-11 Status Register 0 Termination Codes

Status Register 0

Cause

Interrupt

Seek

Code

End

Internal Ready Went True

Normal Seek Termination

Abnormal Seek Termination

Issuing a Sense Interrupt command without an interrupt

pending is treated as an Invalid command If the extended

track range mode is enabled a third byte should be read in

the Result Phase which will indicate the four most signifi-

cant bits of the present track number Otherwise only two

result bytes should be read

4219 Set Track Command

This command is used to inspect or change the value of the

internal Present Track Register This could be useful for re-

covery from disk mis-tracking errors where the real current

track could be read through the Read ID command and

then the Set Track command could be used to set the inter-

nal Present Track Register to the correct value

If the WNR bit is a 0 a track register is to be read In this

case the Result Phase byte contains the value in the inter-

nal register specified and the third byte in the Command

Phase is a dummy byte

If the WNR bit is a 1 data is written to a track register In this

case the third byte of the Command Phase is written to the

specified internal track register and the Result Phase byte

contains this new value

The DS1 and DS0 bits select the Present Track Register for

the particular drive The internal register address depends

on MSB DS1 and DS0 as shown in Table 4-12 This com-

mand does not generate an interrupt

TABLE 4-12 Set Track Register Address

DS1

DS0

MSB

PTR0 (LSB)

PTR0 (MSB)

PTR1 (LSB)

PTR1 (MSB)

PTR2 (LSB)

PTR2 (MSB)

PTR3 (LSB)

PTR3 (MSB)

4220 Specify Command

The Specify command sets the initial values for three inter-

nal timers The function of these Specify parameters is de-

scribed below The parameters of this command are unde-

fined after power up and are unaffected by any reset Thus

software should always issue a Specify command as part of

an initialization routine This command does not generate

an interrupt

The Motor Off and Motor On timers are artifacts of the

PD765 These timers determine the delay from selecting a

drive motor until a read or write operation is started and the

delay of deselecting the drive motor after the command is

completed Since the FDC enables the drive and motor se-

lect line directly through the DOR these timers only provide

some delay from the initiation of a command until it is actu-

ally started

Step Rate Time

These four bits define the time interval

between successive step pulses during a seek implied

seek recalibrate or relative seek The programming of this

step rate is shown in Table 4-13

TABLE 4-13 Step Rate Time (SRT) Values

Data Rate

Value

Range

Units

1 Mbs

(16 b SRT)2

05 – 8

500 kbs

(16 b SRT)

1 – 16

300 kbs

(16 b SRT) c 167

167 – 267

250 kbs

(16 b SRT) c 2

2–32

Motor Off Time

These four bits determine the simulated

Motor Off time as shown in Table 4-14

Motor On Time

These seven bits determine the simulated

Motor On time as shown in Table 4-15

PC87311AVF Datasheet(PDF) 38 Page - National Semiconductor (TI)

PC87311AVF Datasheet(HTML) 38 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL