PC87311AVF datasheet(55/78 Pages) NSC

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60 Serial Ports (Continued)

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character If bit 2 is a logic 0

one Stop bit is generated in the transmitted data

If bit 2 is a logic 1 when a 5-bit data length is

selected one and a half Stop bits are generated

If bit 2 is a logic 1 when either a 6- 7- or 8-bit

word length is selected two Stop bits are generat-

ed The receiver checks the first Stop bit only re-

gardless of the number of Stop bits selected

Bit 3

This bit is the Parity Enable bit When bit 3 is a

logic 1 a Parity bit is generated (transmit data) or

checked (receive data) between the last data bit

and Stop bit of the serial data (The Parity bit is

used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed)

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is a logic 0 an odd number of

logic 1s is transmitted or checked in the data word

bits and Parity bit When parity is enabled and bit 4

is a logic 1 an even number of logic 1s is transmit-

ted or checked

Bit 5

This bit is the Stick Parity bit When parity is en-

abled it is used in conjuction with bit 4 to select

Mark or Space Parity When LCR bits 3 4 and 5

are logic 1 the Parity bit is transmitted and

checked as a logic 0 (Space Parity) If bits 3 and 5

are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 (Mark Pari-

ty) If bit 5 is a logic 0 Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART

When it is set to a logic 1 the serial output (SOUT)

is forced to the Spacing state (logic 0) The break

is disabled by setting bit 6 to a logic 0 The Break

Control bit acts only on SOUT and has no effect

on the transmitter logic

Note

This feature enables the CPU to alert a terminal If the

following sequence is used no erroneous characters will

be transmitted because of the break

1 Wait for the transmitter to be idle (TEMT e 1)

2 Set break for the appropriate amount of time If

the transmitter will be used to time the break

duration then check that TEMT e 1 before

clearing the Break Control bit

3 Clear break when normal transmission has to

be restored

During the break the Transmitter can be used

as a character timer to accurately establish the

break duration by sending characters and moni-

toring THRE and TEMT

Bit 7

This bit is the Divisor Latch Access Bit (DLAB) It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the BOUT signal ap-

pear on the BOUT pin It must be set low (logic 0)

to access any other register

TABLE 6-8 PC87312 UART Reset Configuration

l Signal

Reset Control

Reset State

Interrupt Enable

Master Reset

0000

0000 (Note 1)

Interrupt Identification

Master Reset

0000 0001

FIFO Control

Master Reset

0000 0000

Line Control

Master Reset

0000 0000

MODEM Control

Master Reset

000

0 0000

Line Status

Master Reset

0110 0000

MODEM Status

Master Reset

XXXX

0000 (Note 2)

SOUT

Master Reset

High

INTR (RCVR Errs)

Read LSR

l MR

LowTRI-STATE

INTR (RCVR Data Ready)

Read RBR

l MR

LowTRI-STATE

INTR (THRE)

Read IIR

l Write THR l MR

LowTRI-STATE

INTR (Modem Status Changes)

Read MSR

l MR

LowTRI-STATE

Interrupt Enable Bit

Master Reset

Low

RTS

Master Reset

High

DTR

Master Reset

High

RCVR FIFO

MRFCR1

FCR0 DFCR0

All Bits Low

XMIT FIFO

MRFCR1

FCR0 DFCR0

All Bits Low

Note 1

Boldface bits are permanently low

Note 2

Bits 7–4 are driven by the input signals

PC87311AVF Datasheet(PDF) 55 Page - National Semiconductor (TI)

PC87311AVF Datasheet(HTML) 55 Page - National Semiconductor (TI)

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