PC87311AVF datasheet(51/78 Pages) NSC

51 / 78 page

60 Serial Ports (Continued)

623 Programmable Baud Rate Generator

The PC87311A contains two independently programmable

Baud rate Generators The 24 MHz crystal oscillator fre-

quency input is divided by 13 resulting in a frequency of

18462 MHz This is sent to each Baud rate Generator and

divided by the divisor of the associated UART The output

frequency of the Baud rate Generator (BOUT12) is 16 c

the baud rate

divisor

(frequency input) (baud rate c 16)

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel

Two 8-bit latches per channel store the divisor in a 16-bit

binary format These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator Upon loading either of the Divisor Latches a

16-bit Baud Counter is loaded Table 6-4 provides decimal

divisors to use with crystal frequencies of 24 MHz The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software

Using a divisor of zero is not recommended

TABLE 6-4 PC87311A UART Divisors

Baud Rates and Clock Frequencies

24 MHz Input Divided to 18432 MHz

Baud Rate

Decimal Divisor

Percent

for 16 x Clock

Error

2304

1536

110

1047

1345

857

150

768

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

Note

The percent error for all baud rates except where indicated otherwise

is 02%

624 Line Status Register

This 8-bit register provides status information to the CPU

concerning the data transfer Table 6-2 shows the contents

of the Line Status Register Details on each bit follow

Bit 0

This bit is the receiver Data Ready (DR) indicator Bit

0 is set to logic 1 whenever a complete incoming

character has been received and transferred into the

Receiver Buffer Register Bit 0 is reset to a logic 0 by

reading the data in the Receiver Buffer Register

Bit 1

This bit is the Overrun Error (OE) indicator Bit 1 indi-

cates that data in the Receiver Buffer Register was

not read by the CPU before the next character was

transferred into the Receiver Buffer Register there-

by destroying the previous character The OE indica-

tor is set to a logic 1 upon detection of an overrun

condition and reset whenever the CPU reads the

contents of the Line Status Register

Bit 2

This bit is the Parity Error (PE) indicator Bit 2 indi-

cates that the received data character does not have

the correct even or odd parity as selected by the

even-parity select bit The PE bit is set to a logic 1

upon detection of a parity error and is reset to a logic

0 whenever the CPU reads the contents of the Line

Status Register

Bit 3

This bit is the Framing Error (FE) indicator Bit 3 indi-

cates that the received character did not have a val-

id Stop bit Bit 3 is set to a logic 1 whenever the Stop

bit following the last data bit or parity bit is a logic 0

(Spacing level) The FE indicator is reset whenever

the CPU reads the contents of the Line Status Reg-

ister The UART will try to resynchronize after a

framing error To do this it assumes that the framing

error was due to the next start bit so it samples this

‘‘start’’ bit twice and then takes in the bits following it

as the rest of the frame

Bit 4

This bit is the Break Interrupt (BI) indicator Bit 4 is

set to a logic 1 whenever the received data input is

held in the Spacing (logic 0) state for longer than a

full word transmission time (that is the total time of

Start bit a data bits a Parity a Stop bits) The BI

indicator is reset whenever the CPU reads the con-

tents of the Line Status Register Restarting after a

break is received requires the SIN pin to be logical 1

for at least

bit time

Note

Bits 1 through 4 are the error conditions that produce a

Receiver Line Status interrupt whenever any of the corre-

sponding conditions are detected and the interrupt is en-

abled

Bit 5

This bit is the Transmitter Holding Register Empty

(THRE) indicator Bit 5 indicates that the UART is

ready to accept a new character for transmission In

addition this bit causes the UART to issue an inter-

rupt to the CPU when the Transmiter Holding Regis-

ter Empty Interrupt enable is set high The THRE bit

is set to a logic 1 when a character is transferred

from the Transmitter Holding Register into the

Transmitter Shift Register The bit is reset to logic 0

whenever the CPU loads the Transmitter Holding

Bit 6

This bit changes its function depending on whether

the device is operating in the XT or AT mode When

operating in the AT mode this bit is the Transmitter

Empty (TEMT) indicator Bit 6 is set to a logic 1

whenever the Transmitter Holding Register (THR)

and the Transmitter Shift Register (TSR) are both

empty It is reset to a logic 0 whenever either the

THR or TSR contains a data character When oper-

ating in the XT mode this bit is set whenever the

Transmitter Shift Register is empty It is cleared

whenever a byte is loaded into the Transmit Shift

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