PC87311AVF datasheet(22/78 Pages) NSC

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30 FDC Register Description (Continued)

D1D0 Data Rate Select 10

These bits determine the

data rate for the floppy controller See Table 3-6 for

the corresponding data rate for each value of D1

D0 The data rate select bits are unaffected by a

software reset and are set to 250 kbs after a hard-

ware reset

TABLE 3-6 Data Rate Select Encoding

Data Rate Select

Data Rate

MFM

1 Mbs

Illegal

500 kbs

250 kbs

300 kbs

150 kbs

250 kbs

125 kbs

Note

FM mode is not guaranteed through functional testing

37 DATA REGISTER (FIFO)

ReadWrite

The FIFO (readwrite) is used to transfer all commands

data and status between the mP and the FDC During the

Command Phase the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR During

the Result Phase the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR

The enabling of the FIFO and setting of the FIFO threshold

is done via the Configure command If the FIFO is enabled

only the Execution Phase byte transfers use the 16 byte

FIFO The FIFO is always disabled during the Command

and Result Phases of a controller operation If the FIFO is

enabled it will not be disabled after a software reset if the

LOCK bit is set in the Lock Command After a hardware

reset the FIFO is disabled to maintain compatibility with

PC-AT systems

The 16-byte FIFO can be used for DMA Interrupt or soft-

ware polling type transfers during the execution of a read

write format or scan command In addition the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand In the Burst mode DRQ or IRQ6 remains active until

all of the bytes have been transferred to or from the FIFO In

the Non-Burst mode DRQ or IRQ6 is deasserted for 350 ns

to allow higher priority transfer requests to be serviced The

Mode command can also disable the FIFO for either reads

or writes separately The FIFO allows the system a larger

latency without causing a disk overrununderrun error Typi-

cal uses of the FIFO would be at the 1 Mbs data rate or

with multi-tasking operating systems The default state of

the FIFO is disabled with a threshold of zero The default

state is entered after a hardware reset

Data Register (FIFO)

DESC

Data 70

RESET

Byte Mode

COND

During the Execution Phase of a command involving data

transfer tofrom the FIFO the system must respond to a

data transfer service request based on the following formu-

Maximum Allowable Data Transfer Service Time

(THRESH a 1) c 8 c tDRP b (16 c tICP)

This formula is good for all data rates with the FIFO enabled

or disabled THRESH is a four bit value programmed in the

Configure command which sets the FIFO threshold If the

FIFO is disabled THRESH is zero in the above formula The

last term of the formula (16 c tICP) is an inherent delay due

to the microcode overhead required by the FDC This delay

is also data rate dependent See Table 9-1 for the tDRP and

tICP times

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system In

other words a slow system with a sluggish DMA transfer

capability would use a high value of THRESH giving the

system more time to respond to a data transfer service re-

quest (DRQ for DMA mode or IRQ6 for Interrupt mode)

Conversely a fast system with quick response to a data

transfer service request would use a low value of THRESH

38 DIGITAL INPUT REGISTER (DIR)

Read Only

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals

The function of this register depends on the register mode

of operation When in the PC-AT mode the D6 – D0 are

TRI-STATE to avoid conflict with the fixed disk status regis-

ter at the same address The DIR is unaffected by a soft-

ware reset

381 DIRPC-AT Mode

DESC

DSKCHG

XXXXXXX

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power down this bit will be

invalid if it is read by the software

D6 – D0 Undefined

TRI-STATE Used by Hard Disk Con-

troller Status Register

382 DIRPS2 Mode

DESC

DSKCHG

DRATE1

DRATE0

HIGH

DEN

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power down this bit will be

invalid if it is read by the software

D6 – D3 Reserved

Always 1

D2D1 Data Rate Select 10

These bits indicate the

status of the DRATE10 bits programmed through

the DSR CCR

High Density

This bit is low when the 1 Mbs or

500 kbs data rate is chosen and high when the

300 kbs or 250 kbs data rate is chosen This bit is

independent of the IDENT value

383 DIRModel 30 Mode

D6 D5 D4

DESC

DSKCHG

DMAEN NOPRE DRATE1 DRATE0

RESET

COND

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