TNETV1647GSTZWT datasheet(51/236 Pages) TI1

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TMS320DM6441

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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Table 2-26. HPI Terminal Functions

SIGNAL

TYPE(1)

OTHER(1) (2)

DESCRIPTION

NAME

NO.

Host-Port Interface (HPI)

For EMIFA, this pin is Chip Select 3 output.

EM_CS3

I/O/Z

DVDD18

In HPI mode, this pin must be pulled high via an external 10-k

Ω resistor.

This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, this is the

Bank Address 0 output EM_BA[0]. When connected to an 8-bit asynchronous

EM_BA[0]/

memory, this pin is the lowest order bit of the byte address. When connected to a

DA0/

I/O/Z

DVDD18

16-bit asynchronous memory, this pin has the same function as EMIF address pin

HINT

22 EM_A[22].

For ATA/CF, it is Device address bit 0 output DA0.

In HPI mode, it is the host interrupt output HINT.

This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For EMIFA, this is

Address output EM_A[0], which is the least significant bit on a 32-bit word address.

When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the

EM_A[0]/

address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address.

DA2/

I/O/Z

DVDD18

For ATA/CF, it is Device address bit 2 output DA2.

HCNTL1/

For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine if

GPIO53

address, data, or control information is being transmitted between an external host

and DM6441.

In GPIO mode, it is GPIO53.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. For

EMIFA, this pin is the EM_A[2] address line.

EM_A[2]/

For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

(CLE)/

I/O/Z

DVDD18

In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0

HCNTL0

determine if address, data, or control information is being transmitted between an

external host and DM6441.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. When

EM_A[1]/

used for EMIFA, it is address output EM_A[1].

(ALE)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

HHWIL

In HPI mode, it is Half-word identification input HHWIL.

This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, it is EMIF

EM_R/W/

read/write output EM_R/W.

INTRQ/

I/O/Z

DVDD18

For ATA/CF, it is interrupt request input INTRQ.

HR/W

For HPI, it is the Host Read Write input HR/W. This signal is active high for reads

and low for writes.

This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select

EM_CS2/

2 output EM_CS2 for use with asynchronous memories (i.e. NOR flash) or NAND

I/O/Z

DVDD18

HCS

flash. This is the chip select for the default boot and ROM boot modes.

In HPI mode, this pin is HPI Active Low Chip Select input HCS.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

EM_WE

For EMIFA, it is write enable output EM_WE.

(WE)

For NAND/SmartMedia/xD, it is write enable output (WE).

(IOWR)/

I/O/Z

DVDD18

For CF, it is write strobe output (IOWR).

DIOW/

For ATA, it is write strobe output DIOW.

HDS2

For HPI, it is data strobe 2 input HDS2.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

EM_OE/

For EMIFA, it is output enable output EM_OE.

(RE)/

For NAND/SmartMedia/xD, it is read enable output (RE).

(IORD)/

I/O/Z

DVDD18

For CF, it is read strobe output (IORD).

DIOR/

For ATA, it is read strobe output DIOR.

HDS1

For HPI, it is data strobe 1 input HDS1.

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

EM_WAIT/

For EMIFA, it is wait state extension input EM_WAIT.

(RDY/BSY)/

IPU

I/O/Z

For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).

IORDY/

DVDD18

For ATA/CF, it is IO Ready input IORDY.

HRDY

For HPI, it is ready output HRDY.

(1)

IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-k

Ω resistor should be used.)

(2)

Specifies the operating I/O supply voltage for each signal

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