SPC560P50L5 datasheet(69/112 Pages) STMICROELECTRONICS

69 / 112 page

SPC560P44Lx, SPC560P50Lx

Electrical characteristics

Doc ID 14723 Rev 9

69/112

3.10.4

Input DC electrical characteristics definition

Figure 14 shows the DC electrical characteristics behavior as function of time.

Table 24.

Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)

Symbol

Parameter

Conditions

Value

Unit

Typ

Max

IDD_LV_CORx

RUN—Maximum mode(1)

VDD_LV_CORx

externally forced at 1.3 V

40 MHz

64 MHz

RUN—Typical mode(2)

40 MHz

64 MHz

RUN—Maximum mode(3)

VDD_LV_CORx

externally forced at 1.3 V

64 MHz

HALT mode(4)

VDD_LV_CORx

externally forced at 1.3 V

—1.5

STOP mode(5)

VDD_LV_CORx

externally forced at 1.3 V

—1

IDD_FLASH

Flash during read on single mode

VDD_HV_FL at 3.3 V

—

Flash during erase operation on

single mode

VDD_HV_FL at 3.3 V

—

IDD_ADC

ADC—Maximum mode(1)

VDD_HV_ADC0 at 3.3 V

VDD_HV_ADC1 at 3.3 V

fADC =16MHz

ADC_1

2.5

ADC_0

ADC—Typical mode(2)

ADC_1

0.8

ADC_0 0.005 0.006

IDD_OSC

Oscillator

VDD_OSC at 3.3 V

8 MHz

2.4

Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply

current excluded.

Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.

Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at

PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum frequency,

all peripherals enabled.

Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode, OSC/PLL_0/PLL_1

are OFF, core clock frozen, all peripherals are disabled.

STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF,

OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

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