SPC560P50L5 datasheet(89/112 Pages) STMICROELECTRONICS

89 / 112 page

SPC560P44Lx, SPC560P50Lx

Electrical characteristics

Doc ID 14723 Rev 9

89/112

3.17.2

IEEE 1149.1 interface timing

ttr

CC D

Output transition time

output pin(3)

MEDIUM configuration

CL = 25pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 50pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 100pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 25pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 50pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 100pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

WFRST SR P

RESET input filtered

pulse

——

—

WNFRST SR P

RESET input not

filtered pulse

—

500

—

tPOR

CC D

Maximum delay before

internal reset is

released after all

VDD_HV reach nominal

supply

Monotonic VDD_HV supply ramp

—

|IWPU|CC P

Weak pull-up current

absolute value

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

150

µA

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

150

VDD = 5.0 V ± 10%, PAD3V5V = 1

(4)

—

250

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device

reference manual).

CL includes device and package capacitance (CPKG <5 pF).

The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 38.

RESET electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

Table 39.

JTAG pin AC electrical characteristics

No.

Symbol

Parameter

Conditions

Value

Unit

Min

Max

1tJCYC

D TCK cycle time

—

100

—

2tJDC

D TCK clock pulse width (measured at VDD_HV_IOx/2)

—

3tTCKRISE

D TCK rise and fall times (40% – 70%)

—

4tTMSS, tTDIS CC

D TMS, TDI data setup time

—

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