SPC560P50L5 datasheet(86/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC560P44Lx, SPC560P50Lx

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Doc ID 14723 Rev 9

3.16

AC specifications

3.16.1

Pad AC specifications

Table 36.

Flash memory read access timing

Symbol

Parameter

Conditions(1)

Max value

Unit

fmax

Maximum working frequency at given number of

wait states in worst conditions

2 wait states

MHz

0 wait states

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified

Table 37.

Output pin transition times

Symbol

Parameter

Conditions(1)

Value

Unit

Min Typ Max

ttr

Output transition time output pin(2)

SLOW configuration

CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0

——

TCL = 50 pF

—

100

DCL = 100 pF

—

125

DCL = 25 pF

VDD = 3.3 V ± 10%,

PAD3V5V = 1

——

TCL = 50 pF

—

DCL = 100 pF

—

ttr

Output transition time output pin(2)

MEDIUM configuration

CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

——

TCL = 50 pF

—

DCL = 100 pF

—

DCL = 25 pF

VDD = 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

——

TCL = 50 pF

—

DCL = 100 pF

—

ttr

CC D

Output transition time output pin(2)

FAST configuration

CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

——

CL = 50 pF

—

CL = 100 pF

—

CL = 25 pF

VDD = 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

——

CL = 50 pF

—

CL = 100 pF

—

tSYM

(3)

CC T

Symmetric transition time, same drive

strength between N and P transistor

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified

CL includes device and package capacitances (CPKG < 5 pF).

Transition timing of both positive and negative slopes will differ maximum 50%

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