ST72361AR4-Auto datasheet(64/279 Pages) STMICROELECTRONICS

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Power saving modes

ST72361xx-Auto

64/279

Doc ID 12468 Rev 3

system is enabled, can generate a Watchdog RESET (see Section 22.1: Introduction for

more details).

Figure 25.

HALT timing overview

Figure 26.

HALT mode flow-chart

Note:

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from HALT mode (such as external

interrupt). Refer to Table 16 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=0)

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