ST72361AR4-Auto datasheet(94/279 Pages) STMICROELECTRONICS

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PWM auto-reload timer (ART)

ST72361xx-Auto

94/279

Doc ID 12468 Rev 3

Figure 42.

PWM signal from 0% to 100% duty cycle

11.2.6

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is

generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF

flag must be reset by the user software. This interrupt can be used as a time base in the

application.

11.2.7

External clock and event detector mode

Using the fEXT external prescaler input clock, the auto-reload timer can be used as an

external clock event detector. In this mode, the ARTARR register is used to select the

nEVENT number of events to be counted before setting the OVF flag.

nEVENT = 256 - ARTARR

Caution:

The external clock function is not available in HALT mode. If HALT mode is used in the

application, prior to executing the HALT instruction, the counter must be disabled by clearing

the TCE bit in the ARTCSR register to avoid spurious counter increments.

Figure 43.

External event detector example (3 counts)

11.2.8

Input capture function

Input Capture mode allows the measurement of external signal pulse widths through

ARTICRx registers.

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARTARR

fCOUNTER

=FDh

COUNTER

FDh

FEh

FFh

FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR

fEXT =fCOUNTER

FEh

FFh

FDh

IF OIE = 1

INTERRUPT

IF OIE = 1

ARTCSR READ

=FDh

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